Patents by Inventor De-Wei Yu

De-Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288721
    Abstract: A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Ming-Feng Hsieh, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo, Chien-Chia Cheng
  • Patent number: 12283622
    Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Cheng-Po Chau, Yun Chen Teng
  • Publication number: 20250062139
    Abstract: Embodiments of the present disclosure provide a furnace for semiconductor processing that includes an inner tube defining a reaction chamber and including a sidewall defined along a longitudinal axis of the inner tube and including one or more slits defined through the sidewall in a radial direction with respect to the longitudinal axis. The one or more slits include at least one of a first slit with a width in a range between 10 mm and 100 mm, or a plurality of separate slits with a total number in a range between 2 and 15. The inner tube includes a closed end substantially enclosing the reaction chamber and an open end opposite the closed end with respect to the longitudinal axis. The reaction chamber is configured to be loaded with one or more semiconductor wafers via the open end.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: De-Wei YU, Chien-Chia CHENG, Ming-Hua YU, Hsueh-Chang SUNG, Chii-Horng LI
  • Patent number: 12183590
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20240145581
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11901442
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan, Zheng-Yang Pan, Cheng-Po Chau, Pin-Chu Liang, Hung-Yao Chen, De-Wei Yu, Yi-Cheng Li
  • Publication number: 20230352563
    Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.
    Type: Application
    Filed: June 27, 2023
    Publication date: November 2, 2023
    Inventors: De-Wei Yu, Cheng-Po Chau, Yun Chen Teng
  • Patent number: 11728406
    Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: De-Wei Yu, Cheng-Po Chau, Yun Chen Teng
  • Patent number: 11710777
    Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
  • Publication number: 20230215738
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 11677015
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan, Zheng-Yang Pan, Cheng-Po Chau, Pin-Ju Liang, Hung-Yao Chen, De-Wei Yu, Yi-Cheng Li
  • Patent number: 11605543
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20230011474
    Abstract: A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.
    Type: Application
    Filed: January 17, 2022
    Publication date: January 12, 2023
    Inventors: De-Wei Yu, Ming-Feng Hsieh, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo, Chien-Chia Cheng
  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Publication number: 20220376091
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11444173
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Jin-Mu Yin, Tsung-Chieh Hsiao, Chia-Lin Chuang, Li-Zhen Yu, Dian-Hau Chen, Shih-Wei Wang, De-Wei Yu, Chien-Hao Chen, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui, Min-Hsiu Hung, Hung-Yi Huang, Chun-Cheng Chou, Ying-Liang Chuang, Yen-Chun Huang, Chih-Tang Peng, Cheng-Po Chau, Yen-Ming Chen
  • Publication number: 20220172958
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20220130979
    Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
  • Patent number: 11289343
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 11205709
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu