Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A method includes depositing a silicon layer on a plurality of strips. The silicon layer is etched back to remove top portions of the silicon layer, and to expose some portions of the plurality of strips. Some bottom portions of the silicon layer at bottoms of trenches between the plurality of strips remain after the etching back. A germanium layer is selectively grown from remaining portions of the silicon layer, and exposed portions of the plurality of strips remain exposed after the germanium layer is selectively grown.

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

Abstract: A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench.

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The FIT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

Abstract: Methods and systems that include receiving a plurality of reflectivity measurements on a semiconductor wafer. A reflectivity map is generated based on the received plurality of reflectivity measurements. The generated reflectivity map is used to determine a process parameter of an epitaxial growth process using the reflectivity map. In an embodiment, the process parameter is a power setting (heating) of a lamp of a CVD epitaxy tool.

Abstract: A method of doping a fin field-effect transistor includes forming a plurality of semiconductor fins on a substrate wherein each semiconductor fin of the plurality of semiconductor fins has a top surface and sidewalls. The method includes forming a gate stack over the top surface and sidewalls of each semiconductor fin. The method includes removing a portion of a first semiconductor fin exposed by the gate stack. The method includes growing a first stressor region connected to a remaining portion of the first semiconductor fin. The method includes exposing a second semiconductor fin to a deposition process to form a dopant-rich layer comprising an n-type or a p-type dopant on the top surface and the sidewalls of the second semiconductor fin. The method includes diffusing the dopant from the dopant-rich layer into the second semiconductor fin using an annealing process.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

Abstract: A method of doping a fin field-effect transistor includes forming a plurality of semiconductor fins on a substrate wherein each semiconductor fin of the plurality of semiconductor fins has a top surface and sidewalls. The method includes forming a gate stack over the top surface and sidewalls of each semiconductor fin. The method includes removing a portion of a first semiconductor fin exposed by the gate stack. The method includes growing a first stressor region connected to a remaining portion of the first semiconductor fin. The method includes exposing a second semiconductor fin to a deposition process to form a dopant-rich layer comprising an n-type or a p-type dopant on the top surface and the sidewalls of the second semiconductor fin. The method includes diffusing the dopant from the dopant-rich layer into the second semiconductor fin using an annealing process.

Abstract: A method of doping a FinFET includes forming a semiconductor fin on a substrate, the substrate having a first device region and a second device region. The semiconductor fin is formed on a surface of the substrate in the second device region and has a top surface and sidewalls. The first device region is covered with a hard mask and the semiconductor fin and the hard mask are exposed to a deposition process to form a dopant-rich layer having an n-type or p-type dopant on the top surface and the sidewalls of the semiconductor fin. The dopant from the dopant-rich layer is diffused into the semiconductor fin by performing an annealing process in which the first device region is free of diffusion of the diffused dopant or another dopant from the hard mask.

Abstract: Methods and systems that include receiving a plurality of reflectivity measurements on a semiconductor wafer. A reflectivity map is generated based on the received plurality of reflectivity measurements. The generated reflectivity map is used to determine a process parameter of an epitaxial growth process using the reflectivity map. In an embodiment, the process parameter is a power setting (heating) of a lamp of a CVD epitaxy tool.

Abstract: A method of doping a FinFET includes forming a semiconductor fin on a substrate, the substrate having a first device region and a second device region. The semiconductor fin is formed on a surface of the substrate in the second device region and has a top surface and sidewalls. The first device region is covered with a hard mask and the semiconductor fin and the hard mask are exposed to a deposition process to form a dopant-rich layer having an n-type or p-type dopant on the top surface and the sidewalls of the semiconductor fin. The dopant from the dopant-rich layer is diffused into the semiconductor fin by performing an annealing process in which the first device region is free of diffusion of the diffused dopant or another dopant from the hard mask.