Patents by Inventor Dean E. Probst

Dean E. Probst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200220009
    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Prasad VENKATRAMAN, Dean E. PROBST
  • Patent number: 10600905
    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. The second type of device cell includes a trench that is wider than the trench in the first device cell, but a mesa of the second type of device cell has about the same width as the mesa of the first type of device cell. Having about the same width, the mesa in the second type of device cell in the contact area has similar breakdown characteristics as a mesa in the first type of device cell in the active area of the device.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 24, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Dean E. Probst
  • Publication number: 20200083366
    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. The second type of device cell includes a trench that is wider than the trench in the first device cell, but a mesa of the second type of device cell has about the same width as the mesa of the first type of device cell. Having about the same width, the mesa in the second type of device cell in the contact area has similar breakdown characteristics as a mesa in the first type of device cell in the active area of the device.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Prasad VENKATRAMAN, Dean E. PROBST
  • Publication number: 20190326392
    Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shengling DENG, Dean E. PROBST, Zia HOSSAIN
  • Patent number: 10340372
    Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 2, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Ogura, Mitsuru Soma, Dean E. Probst, Takashi Hiroshima, Peter A. Burke, Toshimitsu Taniguchi
  • Publication number: 20190189788
    Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.
    Type: Application
    Filed: April 3, 2018
    Publication date: June 20, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi OGURA, Mitsuru SOMA, Dean E. PROBST, Takashi HIROSHIMA, Peter A. BURKE, Toshimitsu TANIGUCHI
  • Publication number: 20190067427
    Abstract: A method of forming a shielded gate field effect transistor includes forming a trench within a substrate and depositing a shield oxide material within the trench, which is then recessed. The method further includes depositing a shield electrode material on the shield oxide material and recessing the shield oxide material within the trench to widen an upper portion of the trench. The method further includes recessing the shield electrode material thus forming a recession and depositing an inter-poly oxide material on the shield electrode material into the recession, thus filling the recession. The method further includes forming a gate electrode above the inter-poly oxide material.
    Type: Application
    Filed: December 8, 2017
    Publication date: February 28, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter A. BURKE, Dean E. PROBST, Sallie J. HOSE
  • Publication number: 20180012958
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: August 28, 2017
    Publication date: January 11, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. YEDINAK, Ashok CHALLA, Dean E. PROBST, Daniel KINZER
  • Patent number: 9391193
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: July 12, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
  • Publication number: 20150194521
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: February 23, 2015
    Publication date: July 9, 2015
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
  • Patent number: 8963212
    Abstract: In one general aspsect, a semiconductor device can include at least a first device region and a second device region disposed at a surface of a semiconductor region where the second device region is adjacent to the first device region and spaced apart from the first device region. That semiconductor device can include a connection region disposed between the first device region and the second device region, and a trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region. The semiconductor device can include a dielectric layer lining opposing sidewalls of the trench, an electrode disposed in the trench, and a conductive trace disposed over a portion of the trench in the connection region and electrically coupled to a portion of the electrode disposed in the connection region.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 24, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
  • Patent number: 8936985
    Abstract: A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: January 20, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
  • Patent number: 8932924
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: January 13, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Dean E. Probst, Daniel Calafut
  • Patent number: 8884365
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20140264569
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Joseph A. YEDINAK, Dean E. PROBST, Richard STOKES, Suku KIM, Jason HIGGS, Fred SESSION, Hui CHEN, Steven P. SAPP, Jayson PREECE, Mark L. Rinehimer
  • Publication number: 20140042532
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
  • Publication number: 20140042536
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Dean E. Probst, Daniel Calafut
  • Patent number: 8610205
    Abstract: In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Dean E. Probst
  • Patent number: 8563377
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Daniel Calafut, Dean E. Probst
  • Patent number: 8564024
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst