Patents by Inventor Dean E. Probst
Dean E. Probst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014261Abstract: In a general aspect, a method can include forming well region of one conductivity type in a semiconductor region of another conductivity type An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The method can further include forming at least one dielectric region in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.Type: ApplicationFiled: September 19, 2023Publication date: January 11, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shengling DENG, Dean E. PROBST, Zia HOSSAIN
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Publication number: 20230403003Abstract: A circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) and a snubber circuit coupled between a drain and a source of the MOSFET. The snubber circuit includes a transistor disposed in parallel to the MOSFET. The transistor has a floating gate. The circuit further includes a capacitor in series with the transistor, and a resistor disposed parallel to the capacitor.Type: ApplicationFiled: May 1, 2023Publication date: December 14, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume ROIG-GUITART, Dean E. PROBST, Ashok Challa
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Publication number: 20230352577Abstract: An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.Type: ApplicationFiled: February 17, 2023Publication date: November 2, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Peter MOENS, Balaji PADMANABHAN, Dean E. PROBST, Prasad VENKATRAMAN, Tirthajyoti SARKAR, Gary Horst LOECHELT
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Patent number: 11776997Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.Type: GrantFiled: August 27, 2021Date of Patent: October 3, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shengling Deng, Dean E. Probst, Zia Hossain
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Publication number: 20230282732Abstract: A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.Type: ApplicationFiled: March 2, 2022Publication date: September 7, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Zia HOSSAIN, Dean E. PROBST, Peter A. BURKE, Sauvik CHOWDHURY
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Patent number: 11742420Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.Type: GrantFiled: November 23, 2021Date of Patent: August 29, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Dean E. Probst, Peter A. Burke, Prasad Venkatraman
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Patent number: 11621331Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.Type: GrantFiled: September 10, 2020Date of Patent: April 4, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Publication number: 20220407411Abstract: In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.Type: ApplicationFiled: June 13, 2022Publication date: December 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Dean E. PROBST, Joseph Andrew YEDINAK, Balaji PADMANABHAN, Peter A. BURKE, Jeffery A. NEULS, Ashok CHALLA
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Patent number: 11411077Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.Type: GrantFiled: September 10, 2020Date of Patent: August 9, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Publication number: 20220085204Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Dean E. PROBST, Peter A. BURKE, Prasad VENKATRAMAN
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Publication number: 20220077282Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Applicant: Semiconductor Components Industries, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Publication number: 20220077290Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Applicant: Semiconductor Components Industries, LLCInventors: Gary Horst Loechelt, Balaji Padmanabhan, Dean E. Probst, Tirthajyoti Sarkar, Prasad Venkatraman, Muh-Ling Ger
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Patent number: 11227946Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.Type: GrantFiled: March 20, 2020Date of Patent: January 18, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Prasad Venkatraman, Dean E. Probst
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Patent number: 11217689Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.Type: GrantFiled: August 20, 2019Date of Patent: January 4, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Dean E. Probst, Peter A. Burke, Prasad Venkatraman
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Publication number: 20210391422Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shengling DENG, Dean E. PROBST, Zia HOSSAIN
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Patent number: 11133381Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.Type: GrantFiled: April 23, 2018Date of Patent: September 28, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shengling Deng, Dean E. Probst, Zia Hossain
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Patent number: 11075148Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.Type: GrantFiled: November 6, 2019Date of Patent: July 27, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jeffrey Peter Gambino, David T. Price, Jeffery A. Neuls, Dean E. Probst, Santosh Menon, Peter A. Burke, Bigildis Dosdos
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Patent number: 11049956Abstract: In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed and another material is formed on sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. Source and gate contact openings are formed together.Type: GrantFiled: August 20, 2019Date of Patent: June 29, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Dean E. Probst, Jeffery A. Neuls, Masaichi Eda, Peter A. Burke, Peter McGrath, Prasad Venkatraman
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Publication number: 20210111106Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.Type: ApplicationFiled: November 6, 2019Publication date: April 15, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jeffrey Peter GAMBINO, David T. Price, Jeffery A. NEULS, Dean E. PROBST, Santosh MENON, Peter A. BURKE, Bigildis DOSDOS
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Publication number: 20200395478Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.Type: ApplicationFiled: August 20, 2019Publication date: December 17, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Dean E. PROBST, Peter A. BURKE, Prasad VENKATRAMAN