Patents by Inventor Dean E. Probst

Dean E. Probst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8610205
    Abstract: In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Dean E. Probst
  • Patent number: 8564024
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst
  • Patent number: 8563377
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Daniel Calafut, Dean E. Probst
  • Publication number: 20130248991
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 26, 2013
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Hamza YILMAZ, Daniel CALAFUT, Christopher Boguslaw KOCON, Steven P. SAPP, Dean E. PROBST, Nathan L. KRAFT, Thomas E. GREBS, Rodney S. RIDLEY, Gary M. DOLNY, Bruce D. MARCHANT, Joseph A. YEDINAK
  • Patent number: 8441069
    Abstract: A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 14, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8338285
    Abstract: A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: December 25, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen
  • Patent number: 8278702
    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Scott L. Hunt, Dean E. Probst, Hossein Paravi
  • Publication number: 20120235229
    Abstract: In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 20, 2012
    Inventor: Dean E. Probst
  • Publication number: 20120220091
    Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
    Type: Application
    Filed: March 12, 2012
    Publication date: August 30, 2012
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Publication number: 20120193748
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: April 11, 2012
    Publication date: August 2, 2012
    Inventors: Joseph A. Yedinak, Daniel Calafut, Dean E. Probst
  • Patent number: 8193581
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Dean E. Probst, Ashok Challa, Daniel Calafut
  • Patent number: 8174067
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Daniel Calafut, Dean E. Probst
  • Publication number: 20120104490
    Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 3, 2012
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8148749
    Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: April 3, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Mark Rinehimer, Joseph Yedinak, Dean E. Probst, Gary Dolny, John Benjamin
  • Patent number: 8143124
    Abstract: A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
  • Publication number: 20110275208
    Abstract: A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 10, 2011
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen
  • Patent number: 8044463
    Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: October 25, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Brian S. Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean E. Probst
  • Patent number: 8043913
    Abstract: A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: October 25, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20110177662
    Abstract: A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 7952141
    Abstract: A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: May 31, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen