Patents by Inventor Dean E. Walker

Dean E. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10430190
    Abstract: Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride are disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John D. Leidel, Kevin R. Wadleigh, Joe Bolding, Tony Brewer, Dean E. Walker
  • Publication number: 20130332711
    Abstract: Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride as disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 12, 2013
    Applicant: Convey Computer
    Inventors: John D. Leidel, Kevin R. Wadleigh, Joe Bolding, Tony Brewer, Dean E. Walker
  • Patent number: 8315175
    Abstract: Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: November 20, 2012
    Assignee: Foundry Networks, LLC
    Inventors: Thomas C. McDermott, III, Harry C. Blackmon, Tony M. Brewer, Harold W. Dozier, Jim Kleiner, Gregory S. Palmer, Keith W. Shaw, David Traylor, Dean E. Walker
  • Patent number: 8279879
    Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: October 2, 2012
    Assignee: Foundry Networks, LLC
    Inventors: Tony M. Brewer, Harry C. Blackmon, Chris Davies, Harold W. Dozier, Thomas C. McDermott, III, Steven J. Wallach, Dean E. Walker, Lou Yeh
  • Patent number: 7613183
    Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There are forward error correction (FEC) bytes as well as a chunk cyclical redundancy check (CRC) to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: November 3, 2009
    Assignee: Foundry Networks, Inc.
    Inventors: Tony M. Brewer, Harry C. Blackmon, Chris Davies, Harold W. Dozier, Thomas C. McDermott, III, Steven J. Wallach, Dean E. Walker, Lou Yeh
  • Patent number: 6894970
    Abstract: Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 17, 2005
    Assignee: Chiaro Networks, Ltd.
    Inventors: Thomas C. McDermott, III, Harry C. Blackmon, Tony M. Brewer, Harold W. Dozier, Jim Kleiner, Gregory S. Palmer, Keith W. Shaw, David Traylor, Dean E. Walker
  • Patent number: 6711357
    Abstract: Information and control are synchronized as they flow through a large distributed IP router system with independent clocks. The IP router includes multiple equipment racks and shelves, each containing multiple modules. The IP router is based on a passive switching device, which in some embodiments is an optical switch. Control and data come to the switching device from different sources, which have different clocks. Timing and synchronization control are provided, such that information and control both arrive at the switching device at the proper time. A single point in the system originates timing, which is then distributed through various ASICs of the system to deliver configuration control to the switch at the appropriate time. The launch of information to the switch is also controlled with a dynamic feedback loop from an optical switch controller. Control aspects of the optical switch are aligned by this same mechanism to deliver control and data to the optical switch simultaneously.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: March 23, 2004
    Assignee: Chiaro Networks Ltd.
    Inventors: Tony Brewer, Harry C. Blackmon, Harold W. Dozier, William D. O'Leary, Dean E. Walker