Patents by Inventor Dean E. Walker

Dean E. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220382557
    Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.
    Type: Application
    Filed: August 3, 2022
    Publication date: December 1, 2022
    Inventors: Dean E. Walker, Tony Brewer, Chris Baronne
  • Patent number: 11507453
    Abstract: To implement low-latency register error correction a register may be read as part of an instruction when that instruction is the currently executing instruction in a processor. A correctable error in data produced from reading the register can be detected. In response to detecting the correctable error, the currently executing instruction in the processor can be changed into a register update instruction that is executed to overwrite the data in the register with corrected data. Then, the original (e.g., unchanged) instruction can be rescheduled.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Chris Baronne
  • Publication number: 20220350696
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Dean E. Walker, Tony Brewer
  • Patent number: 11488643
    Abstract: A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer
  • Publication number: 20220300447
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 22, 2022
    Inventors: Dean E. Walker, Tony Brewer
  • Patent number: 11409539
    Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer, Chris Baronne
  • Patent number: 11392448
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer
  • Publication number: 20220222199
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: Dean E. Walker, Tony Brewer
  • Patent number: 11379365
    Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tony Brewer, Dean E. Walker, Chris Baronne
  • Patent number: 11379401
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer
  • Patent number: 11379402
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer
  • Publication number: 20220138142
    Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 5, 2022
    Inventors: Dean E. Walker, Tony M. Brewer
  • Publication number: 20220121452
    Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Dean E. Walker, Tony Brewer, Chris Baronne
  • Publication number: 20220121612
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. Secondary devices on the SPI bus can be configured to include or use respective static identifiers that uniquely identify or address each device. In an example, the primary device can communicate messages using the SPI bus, and the messages can include or use a device identification field. In an example, secondary devices on the SPI bus can be configured to monitor the device identification fields of incoming messages. If a message includes an identification field that corresponds to an identifier of a particular device, then the particular device can attend to the message, and other devices without the same identifier can disregard the message.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Dean E. Walker, Tony Brewer
  • Publication number: 20220121483
    Abstract: Devices and techniques for thread execution control in a barrel processor are described herein. An apparatus includes a barrel processor, which includes local memory including a hazard data structure; and thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including: identifying an instruction to place into a pipeline for the barrel processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a preceding instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on the hazard identification.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Chris Baronne, Dean E. Walker, John Amelio
  • Publication number: 20220121443
    Abstract: Devices and techniques for thread-based processor halting are described herein. A processor monitors control-status register (CSR) values that correspond to a halt condition for a thread. The processor then compares the halt condition to a current state of the thread and halts in response to the current state of the thread meeting the halt condition.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Chris Baronne, Dean E. Walker
  • Publication number: 20220121516
    Abstract: Devices and techniques for low-latency register error correction are described herein. A register is read as part of an instruction when that instruction is the currently executing instruction in a processor. A correctable error in data produced from reading the register can be detected. In response to detecting the correctable error, the currently executing instruction in the processor can be changed into a register update instruction that is executed to overwrite the data in the register with corrected data. Then, the original (e.g. unchanged) instruction can be rescheduled.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Dean E. Walker, Chris Baronne
  • Publication number: 20220123752
    Abstract: A chiplet system comprises an interposer including interconnect and multiple chiplets arranged on the interposer and interconnected using the interconnect of the interposer. The multiple chiplets include a throttle level bus source chiplet including a throttle level bus drive interface configured to place a throttle level value onto the throttle level bus, and one or more throttle level bus receiver chiplets operatively coupled to the throttle level bus. Each chiplet of the multiple chiplets includes throttling logic circuitry configured to set a throttle level of a chiplet according to the throttle level value.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Dean E. Walker, Tony Brewer, David Patrick, Michael Grassi, Bryan Hornung
  • Publication number: 20220121514
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Dean E. Walker, Tony Brewer
  • Publication number: 20220121486
    Abstract: Devices and techniques for rescheduling a failed memory request in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Chris Baronne, Dean E. Walker, John Amelio