Patents by Inventor Dean K. Nobunaga

Dean K. Nobunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861509
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 10832751
    Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Dean K. Nobunaga, Ebrahim Abedifard
  • Publication number: 20200135250
    Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Dean K. Nobunaga, Ebrahim Abedifard
  • Publication number: 20200126601
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 23, 2020
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 10460775
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Publication number: 20190013056
    Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a selection transistor coupled in series between first and second conductive lines. The method includes the steps of precharging the first conductive line; allowing the voltage of the first conductive line to decay toward zero by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level. The discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero.
    Type: Application
    Filed: September 14, 2018
    Publication date: January 10, 2019
    Inventor: Dean K. Nobunaga
  • Publication number: 20180366166
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Publication number: 20180330770
    Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Inventor: Dean K. Nobunaga
  • Patent number: 10127960
    Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 13, 2018
    Assignee: Avalanche Technology, Inc.
    Inventor: Dean K. Nobunaga
  • Patent number: 10083725
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 9921782
    Abstract: The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 20, 2018
    Assignee: Avalanche Technology, Inc.
    Inventor: Dean K. Nobunaga
  • Publication number: 20170345468
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Application
    Filed: August 11, 2017
    Publication date: November 30, 2017
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 9754643
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Publication number: 20170220301
    Abstract: The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 3, 2017
    Inventor: Dean K. Nobunaga
  • Patent number: 9710182
    Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: July 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
  • Publication number: 20160070504
    Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus, The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
  • Publication number: 20160064048
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 9190133
    Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
  • Patent number: 9190153
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 9159373
    Abstract: Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Dean K. Nobunaga