Patents by Inventor Dean K. Nobunaga
Dean K. Nobunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9190133Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.Type: GrantFiled: March 11, 2013Date of Patent: November 17, 2015Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
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Patent number: 9159373Abstract: Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.Type: GrantFiled: July 9, 2013Date of Patent: October 13, 2015Assignee: Micron Technology, Inc.Inventor: Dean K. Nobunaga
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Publication number: 20140258619Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: Micron Technology, Inc.Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
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Publication number: 20140153335Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: ApplicationFiled: October 25, 2013Publication date: June 5, 2014Applicant: Micron Technology, Inc.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Patent number: 8593889Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: GrantFiled: August 21, 2012Date of Patent: November 26, 2013Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Publication number: 20130304984Abstract: The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.Type: ApplicationFiled: July 9, 2013Publication date: November 14, 2013Inventor: Dean K. Nobunaga
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Patent number: 8484428Abstract: The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.Type: GrantFiled: July 30, 2009Date of Patent: July 9, 2013Assignee: Micron Technology, Inc.Inventor: Dean K. Nobunaga
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Publication number: 20120314517Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Patent number: 8248868Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: GrantFiled: April 1, 2011Date of Patent: August 21, 2012Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Publication number: 20110182128Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: ApplicationFiled: April 1, 2011Publication date: July 28, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Patent number: 7920431Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: GrantFiled: June 2, 2008Date of Patent: April 5, 2011Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Publication number: 20110029751Abstract: The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.Type: ApplicationFiled: July 30, 2009Publication date: February 3, 2011Applicant: Micron Technology, Inc.Inventor: Dean K. Nobunaga
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Publication number: 20090300237Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: ApplicationFiled: June 2, 2008Publication date: December 3, 2009Applicant: Micron Technology, Inc.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen