Abstract: A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and thereby achieves a low syndrome bit overhead. The memory controller may write data words to the DRAM having less than 128 bits by first reading 4 32-bit words from the DRAM, substituting the write data for a corresponding number of bits of read data, and writing the new 128-bit word to the DRAM by writing 4 32-bit words.

Abstract: A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The package component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate. A method for fabricating the package component includes the steps of providing a base wafer containing a plurality of base dice, and flip chip mounting the secondary dice to the base dice on the base wafer.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: An unexpanded perlite ore polishing composition is shown. The composition comprises base material having grains of unexpanded perlite ore of a selected distribution of particle sizes which undergo fracturing of the grains as a function of an abrasive force applied to the base material. The selected distribution of particle sizes includes a significant volume of grains of unexpanded perlite ore having a (d90) particle size in a range of about 101 to about 229 ?m. The base material is responsive to an abrasive force being applied thereto during polishing resulting in continued fracturing of the grains of unexpanded perlite ore to yield a final polishing composition having a sufficiently low level of abrasiveness under said abrasive force making it suitable for use in polishing. Compositions for polishing acrylic dentures and CRT tube surfaces using the unexpanded perlite ore polishing composition and methods for polishing the same are also shown.

Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method for compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: One embodiment of the present invention provides an apparatus that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data. Thus, one embodiment of the present invention can be characterized as an apparatus for compressing video data. This apparatus includes a video input port, for receiving video data for a current video frame, and a video input buffer, for storing video data from the video input port. The apparatus additionally includes a previous frame buffer, for storing at least a portion of a previous video frame, as well as an operation unit, for performing an operation between video data from the video input buffer and video data from the previous frame buffer. The embodiment also includes a result buffer coupled to the operation unit, for storing the result of an operation from the operation unit.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

Abstract: A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubbing controller then detects any errors in the read error correcting codes, and generates corrected error correcting codes that are written to the DRAM. This scrubbing procedure, by reading error correcting codes from the DRAM, inherently refreshes memory cells in the DRAM. The error correcting codes are read at rate that may allow data errors to be generated, but these errors are corrected in the memory scrubbing procedure. However, the low rate at which the error correcting codes are read results in a substantial power saving compared to refreshing the memory cells at a higher rate needed to ensure that no data errors are generated.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: A virtual mass storage device implements a data manager for storing information on multiple physical mass storage devices. The virtual mass storage device is organized into blocks of information, which are allocated to different physical devices, thereby enabling the physical devices to operate in parallel and increase the overall transfer rate of the virtual device.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: A computer system includes a central processor unit (“CPU”), a dynamic random access memory (“DRAM”) device, a key storage device storing a decryption key, a decryption engine and a system controller coupling the CPU to the DRAM. All of these components are fabricated on a common integrated circuit substrate so that interconnections between these components are protected from unauthorized access. The system controller is also coupled through to a non-volatile memory that stores a computer program that has been encrypted. In operation, the computer program is transferred through the system controller to the decryption engine, which uses the decryption key to decrypt the computer program. The CPU executes the encrypted program, and, in doing so, transfers data between the CPU and the system memory. This data is protected from unauthorized access because the connections between the CPU and the system memory are internal to the integrated circuit.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

Abstract: A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an arithmetic logic unit, an address multiplexer, and a storage multiplexer. The processor utilizes a data stream containing within it the address for a subsequent instruction to be executed by the processor, thereby avoiding the need for registers of the type utilized in prior art processors. As a result, the processor utilizes a minimal number of registers to perform its operations. The processor utilizes an instruction set in which every instruction contains a JUMP to the next instruction. By utilizing JUMPs in every instruction and providing the address to which the processor is to JUMP, there is no need for address counters and register pointers. Also, extremely fast state changes are facilitated the contents of only one register identifying a next address must be saved or restored.

Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a non-volatile memory. The key may also be derived at least in part from user input to the computer.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.