Abstract: A computer display is disclosed. The computer display includes a LCD housing, a light source coupled to the LCD housing, and a LCD coupled to the LCD housing. The LCD housing conducts light from the light source to the LCD. A method for conducting light is also disclosed. The method includes generating light and conducting the generated light through a LCD housing.

Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a non-volatile memory. The key may also be derived at least in part from user input to the computer.

Abstract: A pliable combined support for decorative lighting comprises a receiver light mount having a light retaining notch and an insert light mount having a light retaining notch. The receiver light mounting bracket assembly is provided with an elongated channel with a tangential extrusion with holes for mounting to a surface or structure and gripping points for receiving lights. The insert light mounting bracket has an elongated insert with a tangential extrusion with holes for mounting to a surface or structure and gripping points for receiving lights. The receiver and insert mounting brackets may be coupled for a rotational frictional attachment whereby the lighting may be displayed in a fixed position along a building, structure, or surface. The receiver and insert mounting brackets can also provide a storage method that will allow lights to be stacked or boxed without tangling.

Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.

Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.

Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.

Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a non-volatile memory. The key may also be derived at least in part from user input to the computer.

Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.

Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.

Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.

Abstract: A pliable combined support for decorative lighting comprises a receiver light mount having a light retaining notch and an insert light mount having a light retaining notch. The receiver light mounting bracket assembly is provided with an elongated channel with a tangential extrusion with holes for mounting to a surface or structure and gripping points for receiving lights. The insert light mounting bracket has an elongated insert with a tangential extrusion with holes for mounting to a surface or structure and gripping points for receiving lights. The receiver and insert mounting brackets may be coupled for a rotational frictional attachment whereby the lighting may be displayed in a fixed position along a building, structure, or surface. The receiver and insert mounting brackets can also provide a storage method that will allow lights to be stacked or boxed without tangling.

Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.

Abstract: Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is formed by applying a force to lateral portions of a liquid material layer formed below an elastomeric material layer such that the liquid material layer has a radius of curvature sufficient to direct light to a light sensitive portion of the device, after which the liquid material layer is exposed to conditions which maintain the radius of curvature after the lateral force is removed.

Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised of a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.