Abstract: Cube polarizers can be designed for substantially equal optical path lengths of a reflected beam and a transmitted beam. For example, d11 of FIG. 1 can define a distance between a plane (face plane2) of the outer face (outer face2) of a second prism 16 and the first edge (first edge1) of the first prism, and d11 can be less than 400 micrometers. As another example, an optical path length differential between a transmitted beam and a reflected beam (|OPLT?OPLR|) can be < 0.5 * t * n p 2 ; where t is a thickness of the substrate between the first surface and the second surface of the substrate and np is an index of refraction of the first prism.

Abstract: Structures and methods of making wire grid polarizers having multiple regions, including side bars, strips, and/or side ribs along sides of a central region. The central region can include a single region or multiple regions. Each region can have a different function for improving polarizer performance. The various regions can support each other for improved wire grid polarizer durability.

Abstract: The cube polarizer can have modified prism dimensions to satisfy the following equation: ? OPL T - OPL R ? < 0.5 * t * n p 2 , where an optical path length is a distance of light travel through a material times an index of refraction of the material, OPLT is an optical path length of the transmitted beam, OPLR is an optical path length of the reflected beam, t is a thickness of the substrate between the first surface and the second surface of the substrate, and np is an index of refraction of the first prism.

Abstract: Structures and methods of making wire grid polarizers having multiple regions, including side bars, strips, and/or side ribs along sides of a central region. The central region can include a single region or multiple regions. Each region can have a different function for improving polarizer performance. The various regions can support each other for improved wire grid polarizer durability.

Abstract: Structures and methods of making wire grid polarizers having multiple regions, including side bars, strips, and/or side ribs along sides of a central region. The central region can include a single region or multiple regions. Each region can have a different function for improving polarizer performance. The various regions can support each other for improved wire grid polarizer durability.

Abstract: Cube polarizers can be designed for substantially equal optical path lengths of a reflected beam and a transmitted beam. For example, d11 of FIG. 1 can define a distance between a plane (face plane2) of the outer face (outer face2) of a second prism 16 and the first edge (first edge1) of the first prism, and d11 can be less than 400 micrometers. As another example, an optical path length differential between a transmitted beam and a reflected beam (|OPLT?OPLR|) can be < 0.5 * t * n p 2 ; where t is a thickness of the substrate between the first surface and the second surface of the substrate and nP is an index of refraction of the first prism.

Abstract: Wire grid polarizers, and methods of making wire grid polarizers, including an array of parallel, elongated nano-structures disposed over a surface of a substrate. Each of the nano-structures can include a first rib disposed over a surface of a substrate and a pair of parallel, elongated wires, each laterally oriented with respect to one another, and disposed over the first rib. The wire grid polarizers can be durable with high transmission of one polarization of light, high contrast, and/or small pitch. The wire grid polarizers can also have high absorption or high reflection of an opposite polarization of light.

Abstract: A wire grid polarizer comprising an array of parallel, elongated nano-structures disposed over a surface of a substrate. Each of the nano-structures can include a pair of parallel, elongated wires (or top ribs), each oriented laterally with respect to one another. There can be a first gap disposed between the pair of wires (or top ribs). Each of the nano-structures can be separated from an adjacent nano-structure by a second gap disposed between adjacent nanostructures, and thus between adjacent pairs of wires. A first gap width of the first gap can be different than a second gap width of the second gap. Also included are methods of making wire grid polarizers.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: Cube polarizers designed for substantially equal optical path lengths of a reflected beam and a transmitted beam. Cube polarizers designed to reduce wire grid polarizer curvature in order to minimize wavefront distortion of the reflected beam and the transmitted beam.

Abstract: Structures and methods of making wire grid polarizers having multiple regions, including side bars, strips, and/or side ribs along sides of a central region. The central region can include a single region or multiple regions. Each region can have a different function for improving polarizer performance. The various regions can support each other for improved wire grid polarizer durability.

Abstract: Wire grid polarizers, and methods of making wire grid polarizers, including an array of parallel, elongated nano-structures disposed over a surface of a substrate. Each of the nano-structures can include a first rib disposed over a surface of a substrate and a pair of parallel, elongated wires, each laterally oriented with respect to one another, and disposed over the first rib. The wire grid polarizers can be durable with high transmission of one polarization of light, high contrast, and/or small pitch. The wire grid polarizers can also have high absorption or high reflection of an opposite polarization of light.

Abstract: A wire grid polarizer comprising an array of parallel, elongated nano-structures disposed over a surface of a substrate. Each of the nano-structures can include a pair of parallel, elongated wires (or top ribs), each oriented laterally with respect to one another. There can be a first gap disposed between the pair of wires (or top ribs). Each of the nano-structures can be separated from an adjacent nano-structure by a second gap disposed between adjacent nanostructures, and thus between adjacent pairs of wires. A first gap width of the first gap can be different than a second gap width of the second gap. Also included are methods of making wire grid polarizers.

Abstract: In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Abstract: A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions.

Abstract: In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Abstract: In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Abstract: A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches.

Abstract: A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions.

Abstract: A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.