Abstract: Method and apparatus for link physical error tracking that includes a one or more shift registers, one or more counters, and a comparator. The shift register receives one or more status bits for an input data stream denoting whether bytes of the input data stream have a link physical error. The counter increments an error count when receiving at least one status bit that denotes a link physical error, and decrements the error count when receiving at least one status bit from an output of the shift register that denotes a link physical error. The comparator compares the error count with a maximum value. A retrain signal is generated if the error count becomes larger than or equal to the maximum value. The retrain signal may be used to signal that a connection between two nodes needs to be retrained to get the two nodes back into synchronization. Link physical errors that occur aligned and misaligned with a rising edge of a symbol clock are trackable.

Abstract: In an error generating circuit and method for generating a 10-bit error character to test 8B/10B decoders, a character generator receives a two-state mode control signal and a two-state disparity control signal and generates a 10-bit error character of a type dependent upon the states of the disparity control signal and the mode control signal. The four types of error characters that can be generated are an invalid 10-bit character having positive disparity, an invalid 10-bit character having negative disparity, a valid 10-bit character having positive disparity, and a valid 10-bit character having negative disparity. A test circuit incorporates the error generating circuit and an 8-bit/10-bit encoder and provides a valid 10-bit character or an 10-bit error character, depending upon the state of an enable signal.