Patents by Inventor Debabrata Gupta
Debabrata Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9496236Abstract: A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.Type: GrantFiled: September 30, 2014Date of Patent: November 15, 2016Assignee: Tessera, Inc.Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Wills Mirkarimi, Rajesh Katkar
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Publication number: 20150014850Abstract: A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Wills Mirkarimi, Rajesh Katkar
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Patent number: 8853558Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.Type: GrantFiled: December 10, 2010Date of Patent: October 7, 2014Assignee: Tessera, Inc.Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Mirkarimi, Rajesh Katkar
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Publication number: 20120145442Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.Type: ApplicationFiled: December 10, 2010Publication date: June 14, 2012Applicant: TESSERA RESEARCH LLCInventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Mirkarimi, Rajesh Katkar
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Patent number: 7535728Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 22, 2006Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 7413936Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.Type: GrantFiled: November 9, 2005Date of Patent: August 19, 2008Assignee: Intel CorporationInventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
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Publication number: 20060279940Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: ApplicationFiled: August 22, 2006Publication date: December 14, 2006Inventors: Kishore Chakravorty, Paul Wermer, David Figueroa, Debabrata Gupta
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Patent number: 7120031Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: July 2, 2004Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Publication number: 20060060946Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.Type: ApplicationFiled: November 9, 2005Publication date: March 23, 2006Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
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Patent number: 7005727Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.Type: GrantFiled: September 3, 2002Date of Patent: February 28, 2006Assignee: Intel CorporationInventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
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Publication number: 20040238942Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: ApplicationFiled: July 2, 2004Publication date: December 2, 2004Applicant: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 6775150Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 30, 2000Date of Patent: August 10, 2004Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Publication number: 20040004232Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.Type: ApplicationFiled: September 3, 2002Publication date: January 8, 2004Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
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Patent number: 5567648Abstract: A method for forming conductive interconnect bumps, such as solder bumps, on bond pads on a substrate. The method includes conductive discs and a connecting member formed between two adjacent conductive discs. The discs and connecting member are then placed over the bond pads and heat is applied so that the conductive discs and the connecting member combine to form isolated interconnect bumps. A polymer backsheet is used for support.Type: GrantFiled: November 3, 1995Date of Patent: October 22, 1996Assignee: Motorola, Inc.Inventor: Debabrata Gupta
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Patent number: 5451274Abstract: A method and apparatus for re-flow of multi-layer metal bumps. A multi layer metal bump structure is surrounded by an oxygen poor environment. The topmost layer of the metal bump structure is heated by using infrared light for a predetermined time. The infrared light has a wavelength which is selected such that the top layer is heated more than the underlying layers.Type: GrantFiled: January 31, 1994Date of Patent: September 19, 1995Assignee: Motorola, Inc.Inventor: Debabrata Gupta
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Patent number: 5341979Abstract: A method and means of bonding a semiconductor die (10) to a support substrate (35) using a thermosonic bonding apparatus (50). The semiconductor die (10) has bonding pads (14, 15, 17) on a first major surface (12), and the support substrate (35) has contact pads (46, 47, 44) on a principal surface (43). Hourglass shaped gold bumps (30) are formed on bonding pads (14, 15, 17). A second major surface (13) of semiconductor die (10) is secured to a thermosonic tool/end-effector (52), and the support substrate (35) is secured to a substrate chuck (48). The hourglass shaped gold bumps (30) are mated with the contact pads ( 46, 47, 44 ) on the support substrate (35). A bond is thermosonically formed between the gold bumps (30) and the contact pads (46, 47, 44).Type: GrantFiled: September 3, 1993Date of Patent: August 30, 1994Assignee: Motorola, Inc.Inventor: Debabrata Gupta
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Patent number: 5198963Abstract: A multi-chip module (26) used to interconnect and house a plurality of integrated circuits (10). The module (26) employs an intermediate structure referred to, herein, as a bridge chip (12). The bridge chip (12) connects the integrated circuit (10) to the module substrate (19). The integrated circuit (10) is attached to the bridge chip (12) and forms a composite structure (18) which can be burned-in and tested as an individual unit. The bridge chip (12) has interconnects to bring out the inputs and outputs of the integrated circuit (10). The composite structure (18) is mounted to the module substrate (19) such that, the integrated circuit (10) has a thermal pathway to the module substrate (19), and the bridge chip (12) connects to the module substrate (19). The module substrate (19) has interconnects to connect the plurality of composite structures (18).Type: GrantFiled: November 21, 1991Date of Patent: March 30, 1993Assignee: Motorola, Inc.Inventors: Debabrata Gupta, James E. Drye
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Patent number: 4773469Abstract: An apparatus and process for continuous horizontal casting of an ingot from molten metal. The apparatus comprises a mold for effecting rapid solidification of the molten metal into the ingot. A feed nozzle supplies the molten metal to the mold. Transition structure is disposed between the mold and the feed nozzle for solidifying the molten metal in the transition structure to prevent freeze back in the feed nozzle.Type: GrantFiled: January 26, 1988Date of Patent: September 27, 1988Assignee: Olin CorporationInventors: Debabrata Gupta, Harvey P. Cheskis
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Patent number: 4564390Abstract: A process is disclosed for reducing the carbon content of a melt of metal or metal alloy, carbon, and at least one strong oxide forming metallic alloying element from an initial value of about 0.1 wt % carbon to a final value of not less than about 0.003 wt % carbon. The process consists of contacting the melt with a reactive oxide of the metallic alloying element and simultaneously stirring the melt with an inert gas.Type: GrantFiled: December 21, 1984Date of Patent: January 14, 1986Assignee: Olin CorporationInventors: Debabrata Gupta, John C. Yarwood
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Patent number: 4472195Abstract: The present invention relates to either a batch or continuous process for decarburization of metals and metal alloys. A shallow melt of metal or metal alloy having a depth of between about 2 in. to about 24 in. is provided. The carbon content of the melt is reduced from its initial value to a range of about 0.3 to 0.1 wt. % carbon. To accomplish this reduction, an oxygen enriched gas is blown onto the surface of the melt at a velocity of about 10 to about 50% of supersonic velocity so as to decarburize the melt without creating any substantial splashing of the melt. At the same time, the melt is stirred by injecting an inert gas below the melt surface. Subsequently, the carbon content of the melt is further reduced from the carbon percentage achieved in the first reduction to a value of not less than about 0.001 wt. % carbon.Type: GrantFiled: August 15, 1983Date of Patent: September 18, 1984Assignee: Olin CorporationInventors: Debabrata Gupta, John C. Yarwood