INTERCONNECT STRUCTURE
A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.
Latest TESSERA RESEARCH LLC Patents:
The present disclosure relates to interconnect structures used in packaged microelectronic assemblies. In particular it relates to interconnect structures used in the connection of microelectronic chips and dies to substrates, such as in flip-chip bonding, or between substrates, such as in the formation of stacked packages. The structures described herein can be used to reduce failure of interconnect bonds due to void formation caused by electromigration between components of prior structures.
Electromigration is a main cause of interconnect failure, especially in high-performance devices where the current density in the interconnect and the device operating temperatures are high. In general, electromigration is caused by the different diffusion rates of materials used in interconnect assemblies. For example, an interconnect assembly can include a contact pad made of copper formed on each of two substrates and a solder mass bonded between the contact pads. The solder mechanically secures the two contact pads, and thus, the substrates on which they are formed, and also electronically connects the two pads so that a signal carried by an electric current can pass between the two pads through the solder mass. In this example, the diffusion rates between the solder and the copper of the pads can be different. The diffusion rates are the rates of molecular movement within the metallic structures over time, and in particular, when subjected to a current or to the heat caused by operation of the devices.
Voids formed in interconnect structures can decrease the reliability of the microelectronic assemblies in which they are used. Further, the presence of voids increases the current density within the materials in the areas surrounding the voids. This can, in turn, further exacerbate the difference in diffusion rate, leading to acceleration of void formation, leading eventually, to both electrical and mechanical failure of the interconnect element.
Present means of decreasing electromigration include using barrier metals or dopants in the solder. These means, however, present their own reliability issues and can lead to cost increases that outweigh their effectiveness. Accordingly, further means for reducing electromigration are needed.
BRIEF SUMMARY OF THE INVENTIONAn embodiment of the present invention relates to a microelectronic assembly. The microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection such that the first surface of the first face is oriented toward the second surface. The first mass extends along an edge of the first projection towards the first dielectric material layer. In a further embodiment, the first fusible metal mass can contact the first dielectric material layer.
The microelectronic assembly can be configured such that the first surface is formed on a substrate and the second surface is formed on a microelectronic element. Additionally or alternatively, the first surface can be formed on a substrate further having a microelectronic element affixed thereon, and the second surface can be formed on a second substrate. In a further embodiment, the microelectronic assembly includes a plurality of interconnect structures each including a first conductive element, a first conductive projections, a second conductive projection, and a first metal mass. Each interconnect structure is connected between the first region of the first face and the second face and has a structure similar to that described above wherein the first dielectric material layer covers the second regions of the thin elements.
The first opening in the first dielectric material layer can define an inside surface such that the inside surface extends along a portion of the first projection in substantial contact therewith. Accordingly, the first dielectric material layer can have a thickness extending in a direction perpendicular to the first face of the first thin element. The thickness can be about 20% to 50% of a height of the first conductive projection.
The base of the first conductive projection can have a periphery such that the second region of the first face is exposed outside of the periphery of the base of the first projection. This arrangement can further form a corner between the first face of the first thin element and the side wall of the first conductive element. The corner can be located along the outer periphery of the base of the first conductive element, and the first dielectric material layer can substantially cover the corner.
In a further embodiment, a second thin conductive element can be exposed on the second surface and can have a second face consisting of first and second regions. The second projection can further have a base that is connected to and covers the first region of the second thin element and defines a periphery and an end portion remote from the base. A second dielectric material layer can cover the second region of the second thin element. Further, the first mass can extend over a portion of the second conductive projection toward the second dielectric material layer.
A further embodiment of the present invention relates to a microelectronic assembly that includes a first surface and a first thin conductive element that is exposed on the first surface and has a face consisting of first and second regions. A first conductive projection is connected to and covers the first region of the first face and extends to an end remote therefrom. The conductive projection has a barrier formed along a portion thereof that has a first edge remote from the first thin conductive element. The assembly further includes a second face having a second conductive projection extending away therefrom. A first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier, the barrier being disposed between the first thin element and the first metal mass. The barrier can be a surface-treatment layer formed in the first conductive projection. The surface-treatment layer can be formed by oxidation or can be a coating applied on a surface of the first conductive projection.
In a still further embodiment, the microelectronic assembly includes a first substrate having a first surface and a first thin conductive element exposed on the first surface and having a first face. A first conductive projection having a base connected to the first face extends to an end remote from the first face and defines a side wall between the base and the end. A dielectric material layer extends along the first surface of the first substrate and has a second surface and a third surface remote from the second surface. The dielectric material layer further has a first opening defining a periphery formed therein. A metal plating layer having a first portion extends along the end and at least a portion of the side wall of the first conductive projection. A second portion of the metal plating layer extends outwardly along a portion of the dielectric material layer and away from the first conductive projection. A first solder mass is formed over at least the first portion of the plating layer and extends toward the third surface.
A still further embodiment relates to microelectronic assembly including a substrate having a first surface, a plurality of first conductive pads exposed on the first surface and defining a face, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to a respective one of the first conductive pads. Each metal post extends along a side wall from the base to ends remote from the first conductive pad. The assembly further includes a dielectric material layer having an inner surface, an outer surface, and a plurality of openings. The inner surface extends along the first surface of the substrate, the outer surface being remote from the substrate. Respective ones of the first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries of the first metal posts. A plurality of fusible metal masses contact the ends of at least some of first metal posts and extend along side walls of the first metal posts towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically connected to at least some of the first conductive pads.
A still further embodiment relates to a microelectronic assembly including a first substrate having a first surface and a first thin conductive element having a first face and being exposed on the first surface. A first conductive projection having a base is connected to the first face and extends to an end remote from the first face. A side wall is defined between the base and the end. The assembly further includes a dielectric material layer having a second surface and a third surface remote from the second surface. The second surface extends along the first surface of the first substrate, and the dielectric material layer has a first opening with a periphery formed therein. A first solder mass is formed on the first conductive projection that extends along the end and a portion of the side wall to a location disposed between the base and the end. The first conductive projection extends through the first opening such that the periphery thereof contacts a portion of the side wall. The solder mass extends towards the third surface of the dielectric material layer.
Turning now to the figures, where like numeric references are used for similar features,
The stacked package 10 of
Each assembly 12,14 also includes a respective microelectronic element 30,32. Microelectronic element 30 is shown affixed to lower substrate 16 by flip-chip bonding, in which microelectronic element 30 is inverted such that its conductive contacts (not shown) face toward upper surface 22. The microelectronic element is then affixed to substrate 16 using conductive projections 34 that extend from its contacts and are bonded using solder masses 36 or another conductive bonding material to second conductive projections 38 formed on substrate 16. Other arrangements are possible for connecting microelectronic element 30 to substrate 16 including face-up mounting, in which the contacts on microelectronic element 30 face away from upper surface 26, adhesive is used to bond microelectronic element 30 to upper surface 26, and wire leads are used to electronically connect the contacts of microelectronic element 30 to conductive features, such as traces or pads, formed on substrate 16. Microelectronic element 32 is shown affixed to substrate 18 in a similar fashion, and can alternatively be attached as described above.
The interconnect structure 50 shown in
A conductive pillar 56 is formed over a portion of face 54 of conductive pad 52. As can be seen in
Interconnect structure 50 further includes a contact pad 64 having a face 66 exposed on lower surface 24 of substrate 18. As with contact pad 52, pad 64 can be embedded in substrate 18 such that face 66 is flush with, above or beneath lower surface 24 so long as face 66 remains exposed thereon. Pad 64 can be connected to conductive features, such as traces or wires, formed on upper surface 26 of substrate 18 using a conductive via 68 formed through substrate 18. In an alternative embodiment, interconnect structure 50 can include a trace or a part of a trace exposed on lower surface 24 in place of pad 64.
A solder mass 70 is used to mechanically and electronically bond pillar 56 to pad 64. During formation and assembly of package 10 solder mass 70 can be formed initially on either pillar 56 or pad 64 and then reflowed when the assemblies 12, 14 are aligned together to allow solder mass 70 to affix to the other of pillar 56 or pad 64. Once in place in package 10, solder mass 70 forms an upper edge 72 and a lower edge 74. Each of upper edge 72 and lower edge 74 can form into a single line or point or a surface. As shown in
The structures and techniques disclosed herein can help reduce electromigration at an interface between pads and a solder mass connecting the pads. Electromigration can pose problems in areas where two or more metallic elements that are in contact with each other exhibit different diffusion rates. In such case, voids formation can occur in the bonding interface. That is, one metal can pull away from the other, forming a gap or opening therebetween.
The use of pillar 56, or another conductive projection, in interconnect structure 50 reduces the distance between the end 62 of pillar 56 and pad 64 along a line of electronic current traveling therebetween when compared to a structure including a solder mass connecting two opposite pads. Accordingly, the structure of
The graphs shown in
The graphs shown in
Accordingly, the presence of a pillar 56 having an end 62 that extends into the solder mass 70 toward a like-metal structure on the other side of the solder mass, such as pad 64 can decrease the likelihood of void formation due to electromigration. This is particularly true in structures that extend through an overall distance 90 that is greater than the distance through which an inter-metallic compound can be expected to extend. In an embodiment where pillar 56 and pad 64 are formed from copper and the solder mass 70 includes tin, the distance 92 between end 62 and face 66 can be between about 10% and 50% of the distance 90. It is noted that while in
In an embodiment, lower edge 74 forms a circular line or annular surface around a portion of the edge surface 60 of pillar 56, which extends into solder mass 70. Further, lower edge 74 is spaced apart from pad 52 such that solder mass 70 does not directly contact any portion of pad 52, including the portion that remains exposed around base 58 of pillar 56. A treatment can be applied to pillar 56, specifically to edge surface 60, near base 58 that can prevent solder mass 70 from wicking along edge surface 60 into contact with face 54 or pad 52. Such treatments can include oxidation or the like. Similarly a layer of material can be applied around edge surface 60 that is resistant to solder flow.
In a further embodiment, lower edge 74 of solder mass 70 is held away from face 54 of pad 52 by a dielectric layer 40 that extends over face 54 and into contact with at least a portion of edge surface 68 adjacent to base 58. In this embodiment, solder mass 70 is allowed to flow into contact with dielectric layer 40, including surface 42, such that lower edge 74 can extend therealong in a spaced-apart relationship with pad 52.
By keeping solder mass 70 away from pad 52, the likelihood of void formation due to electromigration can also be reduced. An interconnect structure of this type reduced electromigration by lowering the concentration of electronic current within solder mass 70. As shown in
As shown in
Dielectric layer 40 is shown in
In an embodiment, dielectric layer 40 has a thickness 42 in the areas covering pads 52 such that the lower end 74 of solder mass 70 is kept spaced apart at a distance therefrom. This distance can include compensation for any tolerance in overall material thickness to ensure that no holes or gaps are present that lead to unintended exposure of face 54 of pad 52. The thickness 42 can be between about 10 μm and 30 μm. In such an embodiment, dielectric layer 40 will have a hole 44 or a plurality of holes 44 through which any interconnect pillars 56 extend. Holes 44 form an inner surface 46 that can contact a portion of edge surface 60 extending upwardly from base 58.
As shown in
Additionally, the inclusion of post 76 in assembly 14 can further decrease the like-metal to like-metal distance within the interconnect structure 70, as described above with respect to
The interconnect structures 50 shown in
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims
1. A microelectronic assembly comprising:
- a first surface;
- a first thin conductive element exposed at the first surface and having a face comprising first and second regions;
- a first conductive projection having a base connected to and covering the first region of the face and extending to an end remote therefrom;
- a first dielectric material layer covering the second region of the first thin element and contacting at least the base of the first conductive projection; and
- a second substrate having a second face and a second conductive projection extending away from the second face; and
- a first fusible metal mass connecting the first projection to the second projection such that the first surface of the first face is oriented toward the second surface, wherein the first mass extends along an edge of the first projection towards the first dielectric material layer.
2. The microelectronic assembly of claim 1, wherein the first surface is formed on a substrate and wherein the second surface is formed on a microelectronic element.
3. The microelectronic assembly of claim 1, wherein the first surface is formed on a substrate further having a microelectronic element affixed thereon, and wherein the second surface is formed on a second substrate.
4. The microelectronic assembly of claim 1, wherein the first fusible metal mass contacts the first dielectric material layer.
5. The microelectronic assembly of claim 1, wherein the first dielectric material layer covers at least a portion of the first surface.
6. The microelectronic assembly of claim 1, wherein the second conductive projection includes an end remote from the second surface, and wherein the end of the first conductive projection is spaced apart from the end of the second conductive projection at a first distance defining a gap therebetween, and wherein the metal mass extends within the gap.
7. The microelectronic assembly of claim 6, wherein the first distance is between 10 and 30 μm.
8. The microelectronic assembly of claim 1, further including a plurality of thin conductive elements exposed on the first surface, each having a face with first and second regions, and a plurality of first conductive projections, each connected to the first region of the first face of a respective one of the plurality of thin elements and extending to an end remote therefrom and a plurality of second conductive projections, each extending away from the second face;
- wherein the first dielectric material layer covers the second regions of the thin elements and a plurality of first fusible metal masses connect respective ones of the first projections to respective ones of the second projections, wherein the respective first mass extends over a portion of the respective first projection toward the first dielectric layer.
9. The microelectronic assembly of claim 1, wherein the first opening in the first dielectric material layer defines an inside surface, and wherein the inside surface extends along a portion of the first projection in substantial contact therewith.
10. The microelectronic assembly of claim 9, wherein the first dielectric material layer has a thickness extending in a direction perpendicular to the first face of the first thin element, and wherein the thickness is between about 10 μm and 30 μm.
11. The microelectronic assembly of claim 9, wherein the first dielectric material layer has a thickness extending in a direction perpendicular to the first face of the thin element, and wherein the thickness is about 20% to 50% of a height of the first conductive projection.
12. The microelectronic assembly of claim 1, wherein the base of the first conductive projection has a periphery, wherein the second region of the first face is exposed outside of the periphery of the base of the first projection.
13. The microelectronic assembly of claim 12, wherein the first projections define a side wall, the side wall being substantially straight along a cross-sectional profile thereof.
14. The microelectronic assembly of claim 13, wherein a corner is formed between the first face of the first thin element and the side wall of the first conductive element, the corner being located along the outer periphery of the base of the first conductive element, and wherein the first dielectric material layer substantially covers the corner.
15. The microelectronic assembly of claim 12, wherein the base of the first conductive projection includes a substantially straight portion extending from the end and a transition portion extending from the outer periphery of the base, the transition portion being substantially arcuate along a cross-sectional profile thereof, and wherein the first dielectric material layer substantially covers the transition portion.
16. The microelectronic assembly of claim 12, wherein the base of the first conductive projection is connected to the first thin element by a layer of conductive metal, the layer of conductive metal having an outside surface substantially aligned with the outer periphery of the base of the first conductive projection, and wherein the first dielectric material layer substantially covers the outside surface of the layer of conductive metal.
17. The microelectronic assembly of claim 1, further including:
- a second thin conductive element exposed on the second surface and having a second face consisting of first and second regions, and wherein the second projection has a base defining a periphery and connected to and covering the first region of the second thin element and an end portion remote from the base;
- a second dielectric material layer covering the second region of the second thin element.
18. The microelectronic assembly of claim 17, wherein the first mass extends over a portion of the second conductive projection toward the second dielectric material layer.
19. The microelectronic assembly of claim 1, wherein the first conductive projection defines a side wall, and wherein a deposited metal layer is formed over the end of the first conductive projection and at least a portion of the side wall thereof.
20. The microelectronic assembly of claim 19, wherein the first dielectric material layer includes an outer surface substantially parallel to the first surface, and the plating layer is further formed with a portion thereof extending outwardly along the outer surface and away from the first conductive projection.
21. The microelectronic assembly of claim 1, wherein the thin element is a substantially circular pad.
22. The microelectronic assembly of claim 21, wherein the first subassembly further includes conductive traces formed on the first substrate and extending from the pad.
23. A microelectronic assembly comprising:
- a first surface;
- a first thin conductive element exposed on the first surface and having a face consisting of first and second regions;
- a first conductive projection connected to and covering the first region of the first face and extending to an end remote therefrom and having a barrier formed along a portion thereof having a first edge remote from the first thin conductive element;
- a second face having a second conductive projection extending away therefrom; and
- a first fusible metal mass connecting the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate, wherein the first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier, the barrier being disposed between the first thin element and the first metal mass.
24. The microelectronic assembly of claim 23, wherein the barrier is a surface-treatment layer formed in the first conductive projection.
25. The microelectronic assembly of claim 24, wherein the surface-treatment layer is formed by oxidation.
26. The microelectronic assembly of claim 24, wherein the surface-treatment layer is a coating applied on a surface of the first conductive projection.
27. The microelectronic assembly of claim 23, wherein the barrier is a layer of dielectric material.
28. The microelectronic assembly of claim 27, wherein the layer of dielectric material covers the second region of the first thin element.
29. A microelectronic assembly, comprising:
- a first subassembly including: a first substrate having a first surface; a plurality of first conductive pads, each having a first face exposed on the first surface; a plurality of first projections, each defining a base having a periphery and connected to a respective one of the first pads, the first projections extending away from the respective first pads, wherein exposed portions of the first faces are defined outside of the peripheries of the bases of the first projections; and a first dielectric material layer overlying the exposed portions of the faces of the first pads, and defining a plurality of openings through which respective ones of the first projections pass, the first dielectric material layer contacting at least the peripheries of the first projections and defining a first outer surface;
- a second subassembly including a second substrate having a second surface, a plurality of second conductive pads exposed on the second surface and a plurality of second projections, each having a base connected to a respective one of the second pads and extending away therefrom; and
- a plurality of fusible metal masses respectively joining the plurality of first connection elements to respective ones of the plurality of second connection elements such that the second face of the second substrate is oriented toward the first face of the first substrate, wherein the fusible metal masses cover at least portions of the first projections extending to the first outer surface of the first dielectric material layer.
30. A microelectronic assembly comprising:
- a first substrate having a first surface;
- a first thin conductive element exposed on the first surface and having a first face;
- a first conductive projection having a base connected to the first face and extending to an end remote from the first face, a side wall being defined between the base and the end;
- a dielectric material layer having a second surface and a third surface remote from the second surface, the second surface extending along the first surface of the first substrate, the dielectric material layer having a first opening defining a periphery formed therein;
- a metal plating layer having a firs portion extending along the end and at least a portion of the side wall of the first conductive projection and a second portion extending outwardly along a portion of the dielectric material layer and away from the first conductive projection; and
- a first solder mass formed over at least the first portion of the plating layer and extending toward the third surface.
Type: Application
Filed: Dec 10, 2010
Publication Date: Jun 14, 2012
Patent Grant number: 8853558
Applicant: TESSERA RESEARCH LLC (San Jose, CA)
Inventors: Debabrata Gupta (Scottsdale, AZ), Yukio Hashimoto (Hitachinaka), Ilyas Mohammed (Santa Clara, CA), Laura Mirkarimi (Sunol, CA), Rajesh Katkar (San Jose, CA)
Application Number: 12/965,192
International Classification: H05K 1/18 (20060101); H05K 1/11 (20060101);