Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Abstract: Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

Abstract: Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.

Abstract: An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.

Abstract: In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.

Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

Abstract: In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: A method for performing a double pass nth fail bitmap of a memory array of a device under test includes a memory built-in test (MBIST) unit reading previously written data from each location of the memory array during a first pass, and detecting a failure associated with a mismatch between written and read data at each location. The method also includes storing within a storage, an address corresponding to a current failing location in response to determining that a predetermined number of locations have failed. The method further includes the MBIST unit reading the previously written data from each location during a second pass. The method includes locking and providing for output, read data stored at a current read address in response to a match between the current read address and any address stored within the storage.

Abstract: A method for performing a double pass nth fail bitmap of a memory array of a device under test includes a memory built-in test (MBIST) unit reading previously written data from each location of the memory array during a first pass, and detecting a failure associated with a mismatch between written and read data at each location. The method also includes storing within a storage, an address corresponding to a current failing location in response to determining that a predetermined number of locations have failed. The method further includes the MBIST unit reading the previously written data from each location during a second pass. The method includes locking and providing for output, read data stored at a current read address in response to a match between the current read address and any address stored within the storage.

Abstract: An apparatus comprises an encode circuit coupled to receive input data and configured to generate corresponding codewords and a decode circuit coupled to receive codewords and detect an error in the codewords (and may, in some cases, correct the error). Each codeword comprises a plurality of b-bit portions (b is an integer greater than one). Additionally, each codeword comprises a first set of b check bits used to detect a magnitude of an error in a b-bit portion of the plurality of b-bit portions. Each codeword further comprises a second set of w check bits used to locate which one of the plurality of b-bit portions is the b-bit portion containing the error (w is an integer greater than zero and less than b).

Abstract: An apparatus comprises an encode circuit coupled to receive input data and configured to generate corresponding codewords and a decode circuit coupled to receive codewords and detect an error in the codewords (and may, in some cases, correct the error). Each codeword comprises a plurality of b-bit portions (b is an integer greater than one). Additionally, each codeword comprises a first set of b check bits used to detect a magnitude of an error in a b-bit portion of the plurality of b-bit portions. Each codeword further comprises a second set of w check bits used to locate which one of the plurality of b-bit portions is the b-bit portion containing the error (w is an integer greater than zero and less than b).

Abstract: A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The input of the first memory is coupled to the first buffer input. The buffer also includes a second memory. The second memory has an input and an output. The input of the second memory is coupled to the second buffer input. The buffer also includes a first register. The first register has an input and an output. The input of the first register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the first register is coupled to the buffer output. The buffer also includes a second register configured to store a second data entry. The second register has an input and an output.