Patents by Inventor Debdeep Jena
Debdeep Jena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894468Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as ?-Ga2O3.Type: GrantFiled: October 30, 2019Date of Patent: February 6, 2024Assignee: Cornell UniversityInventors: Wenshen Li, Zongyang Hu, Kazuki Nomoto, Debdeep Jena, Huili Grace Xing
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Publication number: 20230378276Abstract: The epitaxial growth of ScxAl1-xN—GaN heterostructures and the observation of robust room temperature ferroelectric behavior are disclosed. A semiconductor device, which, for having one or more ScxAl1-xN layers of thicknesses in which ferroelectricity can be observed in the one or more ScxAl1-xN layers, is a nitride ferroelectric transistor (FeFET), which is also disclosed.Type: ApplicationFiled: May 17, 2023Publication date: November 23, 2023Applicant: Cornell UniversityInventors: Joseph Casamento, Ved Gund, Debdeep Jena, Hyunjea Lee Lee, Benyamin Davaji, Amit Lal, Huili (Grace) Xing, Takuya Maeda
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Publication number: 20230326984Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Applicant: Cornell UniversityInventors: Zongyang Hu, Kazuki Nomoto, Grace Huili Xing, Debdeep Jena, Wenshen Li
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Patent number: 11715774Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.Type: GrantFiled: March 28, 2019Date of Patent: August 1, 2023Assignee: Cornell UniversityInventors: Zongyang Hu, Kazuki Nomoto, Grace Huili Xing, Debdeep Jena, Wenshen Li
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Patent number: 11710785Abstract: A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.Type: GrantFiled: June 4, 2020Date of Patent: July 25, 2023Assignee: Cornell UniversityInventors: Austin Hickman, Reet Chaudhuri, Samuel James Bader, Huili Grace Xing, Debdeep Jena
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Publication number: 20230197883Abstract: A method for achieving voltage-controlled gate-modulated light emission using monolithic integration of fin- and nanowire-n-i-n vertical FETs with bottom-tunnel junction planar InGaN LEDs is described. This method takes advantage of the improved performance of bottom-tunnel junction LEDs over their top-tunnel junction counterparts, while allowing for strong gate control on a low-cross-sectional area fin or wire without sacrificing LED active area as in lateral integration designs. Electrical modulation of 5 orders, and an order of magnitude of optical modulation are achieved in the device.Type: ApplicationFiled: July 13, 2021Publication date: June 22, 2023Applicant: Cornell UniversityInventors: Shyam Bharadwaj, Kevin Lee, Kazuki Nomoto, Austin Hickman, Len van Deurzen, Huili Grace Xing, Debdeep Jena, Vladimir Protasenko
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Publication number: 20230054128Abstract: Disclosed are ferroelectric devices including devices for performing a multiplication of analog input signals and resonators. In one aspect, a ferroelectric nanoelectromechanical device includes a first structural beam, a first input electrode disposed on a first top portion of the first structural beam, and an output electrode. The apparatus further includes a first ferroelectric film disposed on a second top portion of the first input electrode, and a first resistive layer disposed on a third top portion of the first ferroelectric film, wherein a first electrode is positioned at a first end of the first resistive layer and a second electrode is positioned at a second end of the first resistive layer.Type: ApplicationFiled: August 23, 2022Publication date: February 23, 2023Inventors: Amit LAL, Shubham JADHAV, Ved GUND, Benyamin DAVAJI, Grace XING, Debdeep JENA
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Patent number: 11522080Abstract: III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.Type: GrantFiled: November 6, 2019Date of Patent: December 6, 2022Assignee: Cornell UniversityInventors: Samuel James Bader, Reet Chaudhuri, Huili Grace Xing, Debdeep Jena
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Patent number: 11476383Abstract: A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.Type: GrantFiled: January 31, 2019Date of Patent: October 18, 2022Assignee: Cornell UniversityInventors: Henryk Turski, Debdeep Jena, Huili Grace Xing, Shyam Bharadwaj, Alexander Austin Chaney, Kazuki Nomoto
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Publication number: 20220294189Abstract: Tunnel junctions (TJs) are used to invert a relative arrangement of the built-in polarization and current flow direction for metal (Ill)-polar grown Ill-nitride laser diodes (LDs). The resulting devices has subsequent TJ, p-type layers, active region and n-type layers. This arrangement ensures a band alignment which provides an injection efficiency of 100% without the need of close proximity of an electron blocking layer.Type: ApplicationFiled: April 1, 2020Publication date: September 15, 2022Inventors: Henryk Turski, Grzegorz MUZIOL, Marcin SIEKACZ, Czeslaw SKIERBISZEWSKI, Debdeep Jena, Huili Grace Xing
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Publication number: 20220199782Abstract: Gallium nitride high-electron-mobility transistors (GaN HEMTs) are at a point of rapid growth in defense (radar, SATCOM) and commercial (5G and beyond) industries. This growth also comes at a point at which the standard GaN heterostructures remain unoptimized for maximum performance. For this reason, the shift to the aluminum nitride (AlN) platform is disclosed. AlN allows for smarter, highly-scaled heterostructure design that improves the output power and thermal management of GaN amplifiers. Beyond improvements over the incumbent amplifier technology, AlN allows for a level of integration previously unachievable with GaN electronics. State-of-the-art high-current p-channel FETs, mature filter technology, and advanced waveguides, all monolithically integrated with an AlN/GaN/AlN HEMT, is made possible with aluminum nitride. It is on this AlN platform that nitride electronics may maximize their full high-power, highspeed potential for mm-wave communication and high-power logic applications.Type: ApplicationFiled: December 17, 2021Publication date: June 23, 2022Applicant: Cornell UniversityInventors: Austin Hickman, Reet Chaudhuri, James C. M. Hwang, Huili Grace Xing, Debdeep Jena
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Publication number: 20210384362Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the re-quirements unique to Group III trioxides, such as ?-Ga2O3.Type: ApplicationFiled: October 30, 2019Publication date: December 9, 2021Applicant: Cornell UniversityInventors: Wenshen Li, Zongyang Hu, Kazuki Nomoto, Debdeep Jena, Huili Grace Xing
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Patent number: 11043612Abstract: A DUV-LED including a bottom substrate, a n-contact/injection layer formed on the bottom substrate, a p-contact region, and an emitting active region between the n-contact/injection layer and the contact region. The emitting active region includes at least one GaN quantum heterostructure. The at least one GaN quantum heterostructures is sized and shaped to determine a certain emission wavelength. Preferably, the certain emission wavelength is in a range of approximately 219-280 nm. In one embodiment, the size is controlled by precisely controlling parameters selected from the group consisting of: an epitaxial deposition time; a Ga/N ratio; a thermal annealing time; a temperature during deposition; and combinations thereof.Type: GrantFiled: November 15, 2018Date of Patent: June 22, 2021Assignee: Cornell UniversityInventors: SM Islam, Vladimir Protasenko, Huili Grace Xing, Debdeep Jena, Jai Verma
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Patent number: 10957817Abstract: A polarization field assisted DUV-LED including a bottom substrate and a n-contact/injection layer formed on the bottom substrate. The n-contact/injection layer includes: a first region for accommodating strain relaxation; a second region for lateral access with a low sheet resistance and higher conductivity compared to the first region to minimize resistive losses and heat generation; and a third region of a graded vertical injection layer with low vertical resistance to minimize heat loss due to vertical resistance. The DUV-LED also includes a p-contact region, and an emitting active region between the n-contact/injection layer and the p-contact region. The injection of electrons and holes into quantum wells proceeds due to tunneling of electrons and holes under the barriers due to less than 2 nm thickness of barriers. This carrier injection lowers the Turn ON voltage of LEDs and reduces heat generation.Type: GrantFiled: November 15, 2018Date of Patent: March 23, 2021Assignee: Cornell UniversityInventors: Sm Islam, Vladimir Protasenko, Huili Grace Xing, Debdeep Jena
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Publication number: 20210043795Abstract: A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.Type: ApplicationFiled: January 31, 2019Publication date: February 11, 2021Applicant: Cornell UniversityInventors: Henryk Turski, Debdeep Jena, Huili Grace Xing, Shyam Bharadwaj, Alexander Austin Chaney, Kazuki Nomoto
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Publication number: 20210043824Abstract: Solid-state devices including a layer of a superconductor material epitaxially grown on a crystalline high thermal conductivity substrate, the superconductor material being one of TiNx, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or alloys thereof, and one or more layers of a semiconducting or insulating or metallic material epitaxially grown on the layer of superconductor material, the semiconducting or insulating material being one of a Group III N material or alloys thereof or a Group 4b N material or SiC or ScN or alloys thereof.Type: ApplicationFiled: March 6, 2019Publication date: February 11, 2021Applicants: Cornell University, The Government of the United States of America, as represented by the Secretary of the NavyInventors: Rusen Yan, Guru Bahadur Singh Khalsa, John Wright, H. Grace Xing, Debdeep Jena, D. Scott Katzer, Neeraj Nepal, Brian P. Downey, David J. Meyer
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Publication number: 20210013314Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.Type: ApplicationFiled: March 28, 2019Publication date: January 14, 2021Applicant: Cornell UniversityInventors: Zongyang Hu, Kazuki Nomoto, Grace Huili Xing, Debdeep Jena, Wenshen Li
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Publication number: 20200388701Abstract: A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.Type: ApplicationFiled: June 4, 2020Publication date: December 10, 2020Inventors: Austin Hickman, Reet Chaudhuri, Samuel James Bader, Huili Grace Xing, Debdeep Jena
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Publication number: 20200144407Abstract: III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.Type: ApplicationFiled: November 6, 2019Publication date: May 7, 2020Applicant: Cornell UniversityInventors: Samuel James Bader, Reet Chaudhuri, Huili Grace Xing, Debdeep Jena
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Publication number: 20190148584Abstract: A DUV-LED including a bottom substrate, a n-contact/injection layer formed on the bottom substrate, a p-contact region, and an emitting active region between the n-contact/injection layer and the contact region. The emitting active region includes at least one GaN quantum heterostructure. The at least one GaN quantum heterostructures is sized and shaped to determine a certain emission wavelength. Preferably, the certain emission wavelength is in a range of approximately 219-280 nm. In one embodiment, the size is controlled by precisely controlling parameters selected from the group consisting of: an epitaxial deposition time; a Ga/N ratio; a thermal annealing time; a temperature during deposition; and combinations thereof.Type: ApplicationFiled: November 15, 2018Publication date: May 16, 2019Applicants: Cornell University, University of Notre Dame du LacInventors: SM Islam, Vladimir Protasenko, Huili Grace Xing, Debdeep Jena, Jai Verma