Patents by Inventor Debendra Das Sharma

Debendra Das Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190196991
    Abstract: Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Publication number: 20190188178
    Abstract: Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
    Type: Application
    Filed: September 17, 2018
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Debendra Das Sharma
  • Patent number: 10296399
    Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Publication number: 20190149265
    Abstract: Systems and devices can include a first port of a first device coupled to a second port of a second device across a multi-lane link. The first port can augment a data block with error correcting code by distributing error correcting code evenly across each lane of the data block, wherein each lane of the data block includes a same number of error correcting code. The first port can transmit the data block with the per-lane error correcting code to the second port across the multi-lane link. The second port can determine error correcting code based on the error correcting code bits received in the data block, and perform error correction on the symbols of the data block based on the error correcting code received.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Publication number: 20190131974
    Abstract: A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 2, 2019
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Publication number: 20190108124
    Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line.
    Type: Application
    Filed: September 24, 2018
    Publication date: April 11, 2019
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
  • Patent number: 10250436
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices for error handling of data received across a multi-Lane Link compliant with a Peripheral Component Interconnect Express (PCIe) protocol. The system can include an upstream device to transmit a data packet across a multi-Lane Link compliant with the PCIe protocol and a downstream device connected to the upstream device across a multi-Lane Link, the downstream device comprising a receiver that comprises a deframer logic. The deframer logic can identify a Framing error in a received data packet received on one Link of the multi-Lane Link; determine that one or more other data packets received on one or more other Links of the multi-Lane Link do not present a Framing error; and process the received data packet based on the one or more other data packets received on the one or more other Links.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 10248591
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20190095380
    Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 28, 2019
    Inventor: Debendra Das Sharma
  • Patent number: 10229024
    Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Publication number: 20190065415
    Abstract: Technologies for providing local disaggregation of memory include a compute sled. The compute sled includes a compute engine having a processor. The compute engine receives a request to perform a memory access operation on data residing in a first memory (e.g., a storage class memory) of the compute sled. The compute engine determines whether the data is cached in a second memory (e.g., a dynamic random-access memory (DRAM)). The compute engine performs, in response to a determination that the data is not cached in the second memory via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.
    Type: Application
    Filed: March 9, 2018
    Publication date: February 28, 2019
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar, Mohamed Arafa, Suresh Chittor, Debendra Das Sharma, Pankaj Kumar
  • Publication number: 20190065426
    Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
  • Publication number: 20190065272
    Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 28, 2019
    Inventors: Anil Rao, Debendra Das Sharma
  • Publication number: 20190042511
    Abstract: An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Inventors: Murugasamy K. NACHIMUTHU, Mark A. SCHMISSEUR, Dimitrios ZIAKAS, Debendra DAS SHARMA, Mohan J. KUMAR
  • Publication number: 20190042380
    Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
    Type: Application
    Filed: May 25, 2018
    Publication date: February 7, 2019
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • Publication number: 20190041898
    Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
    Type: Application
    Filed: March 13, 2018
    Publication date: February 7, 2019
    Inventors: David J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
  • Publication number: 20190042524
    Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 10198394
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Publication number: 20190034376
    Abstract: Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.
    Type: Application
    Filed: November 14, 2017
    Publication date: January 31, 2019
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 10191877
    Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Manjari Kulkarni, Akshay G. Pethe, Sean O. Stalley, Mahesh Wagh, Debendra Das Sharma