Patents by Inventor Debendra Das Sharma

Debendra Das Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flit-based packetization
    Patent number: 11429553
    Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme. The assembled flits can be transmitted across one or more serial point-to-point interconnects in a link connecting the transmitting device to a receiving device. The protocol stack can protect flit information sent across each point-to-point interconnect with a lane-level interleaved forward error correction (FEC) scheme.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT
    Publication number: 20220271912
    Abstract: Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 12, 2022
    Publication date: August 25, 2022
    Inventors: Gerald Pasdast, Peipei Wang, Lakshmipriya Seshan, Juan Zeng, Zuoguo Wu, Zhiguo Qian, Narasimha Lanka, Debendra Das Sharma, Swadesh Choudhary
  • RECALIBRATION OF PHY CIRCUITRY FOR THE PCI EXPRESS (PIPE) INTERFACE BASED ON USING A MESSAGE BUS INTERFACE
    Publication number: 20220269641
    Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.
    Type: Application
    Filed: May 6, 2022
    Publication date: August 25, 2022
    Applicant: Intel Corporation
    Inventors: Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Fulvio Spagna, Bruce A. Tennant, Noam Dolev Geldbard
  • VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS
    Publication number: 20220261308
    Abstract: Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Inventors: Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Swadesh Choudhary, Zuoguo Wu, Gerald Pasdast
  • CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS
    Publication number: 20220262756
    Abstract: Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Inventors: Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu, Swadesh Choudhary
  • PCI EXPRESS ENHANCEMENTS
    Publication number: 20220255559
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 11, 2022
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT
    Publication number: 20220237138
    Abstract: In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 28, 2022
    Inventors: Narasimha Lanka, Lakshmipriya Seshan, Swadesh Choudhary, Debendra Das Sharma, Zuoguo Wu, Gerald Pasdast
  • Retimer mechanisms for in-band link management
    Patent number: 11397701
    Abstract: A retimer apparatus can include a receiver circuit implemented at least partially in hardware; a configuration register comprising a link management bit set, and one or more bit fields for link management bits indicating link management information; bit stream logic implemented at least partially in hardware to encode an ordered set (OS) with one or more link management bits from the configuration register; and a transmitter circuit implemented at least partially in hardware to transmit OS with the one or more link management bits across a link.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS
    Publication number: 20220222198
    Abstract: In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: Narasimha Lanka, Swadesh Choudhary, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast
  • Extending multichip package link off package
    Patent number: 11386033
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • FLIT-BASED PARALLEL-FORWARD ERROR CORRECTION AND PARITY
    Publication number: 20220147417
    Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Cross-talk generation in a multi-lane link during lane testing
    Patent number: 11327861
    Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface
    Patent number: 11327920
    Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Fulvio Spagna, Bruce A. Tennant, Noam Dolev Geldbard
  • SYSTEM, APPARATUS AND METHODS FOR PERFORMING SHARED MEMORY OPERATIONS
    Publication number: 20220114098
    Abstract: In an embodiment, an apparatus for memory access may include: a memory comprising at least one atomic memory region, and a control circuit coupled to the memory, The control circuit may be to: for each submission queue of a plurality of submission queues, identify an atomic memory location specified in a first entry of the submission queue, wherein each submission queue is to store access requests from a different requester; determine whether the atomic memory location includes existing requester information; and in response to a determination that the atomic memory location does not include existing requester information, perform an atomic operation for the atomic memory location based at least in part on the first entry of the submission queue. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Debendra Das Sharma, Robert Blankenship
  • SYSTEM, APPARATUS AND METHODS FOR DIRECT DATA READS FROM MEMORY
    Publication number: 20220114099
    Abstract: In an embodiment, a system may include an interconnect device comprising first, second, and third ports; a first processor coupled to the first port; a second processor coupled to the second port; and a system memory coupled to the third port. The interconnect device may be to: receive, from the first processor via the first port, a speculative read request for a data element stored in the system memory, where coherence of the data element is managed by the second processor, receive a direct read request for the data element, merge the direct read request with the speculative read request, and transmit the data element directly to the first processor via the first port. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Robert Blankenship, Debendra Das Sharma
  • HIGH PERFORMANCE INTERCONNECT
    Publication number: 20220114122
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • LATENCY OPTIMIZATION IN PARTIAL WIDTH LINK STATES
    Publication number: 20220116138
    Abstract: A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventor: Debendra Das Sharma
  • Enabling Sync Header Suppression Latency Optimization In The Presence Of Retimers For Serial Interconnect
    Publication number: 20220114128
    Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
  • Ordered sets for high-speed interconnects
    Patent number: 11296994
    Abstract: A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Adjustable retimer buffer
    Patent number: 11288154
    Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich