Patents by Inventor Debendra Mallik

Debendra Mallik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210082826
    Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Vipul Vijay MEHTA, Eric Jin LI, Sanka GANESAN, Debendra MALLIK, Robert Leon SANKMAN
  • Publication number: 20210043570
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20210035911
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20210035881
    Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
  • Patent number: 10910317
    Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Vipul Vijay Mehta, Eric Jin Li, Sanka Ganesan, Debendra Mallik, Robert Leon Sankman
  • Publication number: 20210028080
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Srinivas PIETAMBARAM, Robert L. Sankman, Rahul Manepalli, Gang Duan, Debendra Mallik
  • Publication number: 20210013188
    Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Sanka Ganesan, DOUG INGERLY, ROBERT SANKMAN, MARK BOHR, DEBENDRA MALLIK
  • Publication number: 20210005542
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 7, 2021
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Rahul MANEPALLI, Srinivas PIETAMBARAM
  • Publication number: 20200411464
    Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Sergio Antonio Chan Arguedas, Jimin Yao, Chandra Mohan Jha
  • Publication number: 20200395300
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Biancun Xie, Jianyong Xie, Sujit Sharan, Debendra Mallik, Robert L. Sankman
  • Publication number: 20200395313
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Shawna LIFF, Srinivas PIETAMBARAM, Bharat PENMECHA
  • Publication number: 20200395297
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 17, 2020
    Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
  • Patent number: 10847467
    Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Debendra Mallik, Mathew J. Manusharow, Jianyong Xie
  • Publication number: 20200350181
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: November 5, 2020
    Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Debendra MALLIK, Bassam M. ZIADEH, Yoshihiro TOMITA
  • Publication number: 20200335443
    Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Xiao Di SUN ZHOU, Debendra MALLIK, Xiaoying GUO
  • Publication number: 20200328151
    Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Amruthavalli Pallavi Alur, Debendra Mallik
  • Patent number: 10796988
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Publication number: 20200312767
    Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Srinivas V. Pietambaram, Tarek Ibrahim, Kristof Darmawikarta, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman
  • Publication number: 20200286814
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Ravindranath MAHAJAN, Debendra MALLIK, Sujit SHARAN, Digvijay RAORANE
  • Publication number: 20200273784
    Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.
    Type: Application
    Filed: December 30, 2017
    Publication date: August 27, 2020
    Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI