Patents by Inventor Debendra Mallik

Debendra Mallik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711441
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Mihir Roy
  • Patent number: 9691727
    Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Javier Soto Gonzalez, Charavana K. Gurumurthy, Robert M. Nickerson, Debendra Mallik
  • Publication number: 20170178990
    Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Sasha Oster, Srikant Nekkanty, Joshua D. Heppner, Adel A. Elsherbini, Yoshihiro Tomita, Debendra Mallik, Shawna M. Liff, Yoko Sekihara
  • Publication number: 20170170105
    Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Sanka Ganesan, Shawna M. Liff, Yikang Deng, Debendra Mallik
  • Patent number: 9679843
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Publication number: 20170154842
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 25, 2014
    Publication date: June 1, 2017
    Inventors: Mathew J. MANUSHAROW, Dustin P. WOOD, Debendra MALLIK
  • Publication number: 20170108655
    Abstract: A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Edward A. ZARBOCK, Debendra MALLIK
  • Publication number: 20170103970
    Abstract: 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: Debendra Mallik, Robert L. Sankman
  • Patent number: 9570883
    Abstract: A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: February 14, 2017
    Assignee: INTEL CORPORATION
    Inventors: Edward A. Zarbock, Debendra Mallik
  • Patent number: 9526285
    Abstract: A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 27, 2016
    Assignee: INTEL CORPORATION
    Inventors: Aleksandar Aleksov, Ravindranath V. Mahajan, Sairam Agraharam, Ian A. Young, John C. Johnson, Debendra Mallik, John S. Guzek
  • Patent number: 9530758
    Abstract: 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Robert L. Sankman
  • Patent number: 9526175
    Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Mathew J. Manusharow, Mihir K. Roy, Kaladhar Radhakrishnan, Debendra Mallik, Edward A. Burton
  • Patent number: 9478476
    Abstract: A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Sridhar Narasimhan, Mathew J. Manusharow, Thomas A. Boyd
  • Publication number: 20160268231
    Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.
    Type: Application
    Filed: September 15, 2014
    Publication date: September 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh
  • Patent number: 9391013
    Abstract: 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ram S. Viswanath, Sriram Srinivasan, Mark T. Bohr, Andrew W. Yeoh, Sairam Agraharam
  • Publication number: 20160197065
    Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 7, 2016
    Inventors: John S. Guzek, Debendra Mallik, Sasha N. Oster, Timothy E. McIntosh
  • Publication number: 20160197037
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: February 22, 2016
    Publication date: July 7, 2016
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Publication number: 20160181218
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Publication number: 20160155694
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 2, 2016
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Mihir Roy
  • Patent number: 9355242
    Abstract: Managing and accessing personal data is described. In one example, an apparatus has an application processor, a memory to store data, a receive and a transmit array coupled to the application processor to receive data to store in the memory and to transmit data stored in the memory through a wireless interface, and an inertial sensor to receive user commands to authorize the processor to receive and transmit data through the receive and transmit array.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Kelin J. Kuhn, Debendra Mallik, John C. Johnson