Patents by Inventor Debendra Mallik

Debendra Mallik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5685477
    Abstract: Methods for soldering a ball grid array (BGA) integrated circuit package to a printed circuit board. One method includes the steps of applying a solder flux to the conductive surface pads of a printed circuit board and capturing a plurality of solder balls with a separate fixture. The fixture is then placed onto the printed circuit board and the solder balls are released onto the conductive surface pads. The fixture is removed and an integrated circuit package is placed onto the solder balls. Solder flux may be applied to the bottom of the package to adhere the package to the balls. The solder balls are then reflowed to attach the package to the board. The flux provides a bonding agent which maintains the position of the solder balls and package while the solder is being reflowed. Another method includes the step of placing a fixture adjacent to the integrated circuit package so that a plurality of openings in the fixture are aligned with surface pads located on the bottom surface of the package.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: November 11, 1997
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Joni Hansen, Ashok K. Seth, Neil R. Sugai
  • Patent number: 5557502
    Abstract: An integrated circuit package which has internal bonding pads that are located on bonding shelves and coupled to internal conductive power/ground planes by conductive strips that extend along the edges of the shelves. The edge strips eliminate the need for conventional vias to couple the bonding pads to the planes and thus reduce the cost and size of the package and improve package electrical performance (less inductive, less resistance path). The bonding pads are coupled to an integrated circuit that is mounted to a heat slug attached to a top surface of the package. The heat slug can function as both a ground path and a thermal sink for the integrated circuit. The package may have capacitors coupled to the internal routing of the package to reduce the electrical noise of the signals provided to the integrated circuit. Additionally, the package may have multiple power planes dedicated to different voltage levels.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: September 17, 1996
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Debendra Mallik, Ashok Seth
  • Patent number: 5556807
    Abstract: A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of conductive material with the leads of the lead frame.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: September 17, 1996
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Debendra Mallik, Syunsuke Ban, Takatoshi Takikawa, Shosaku Yamanaka
  • Patent number: 5519580
    Abstract: A ball grid array (BGA) package which has a plurality of solder balls attached to solder landings that each have a number of tabs which extend from a center area of the landing. The tabs assist in a symmetric formation of solder balls that are formed on the landings. When constructing the package, a solder mask is applied to a bottom package surface before the application of the solder balls. The solder mask has a plurality of openings which expose the solder landings and are larger than the center area of the landings. Solder balls are then placed onto the solder landings and reflowed so that the balls become attached to the landings. The fully exposed center areas of the solder landings allow the solder to flow vertically along the outer walls of the landings, thereby providing a more robust solder joint. The exposed solder landings also allow a solder flux to be thoroughly cleaned after the solder balls are attached to the landings.
    Type: Grant
    Filed: September 9, 1994
    Date of Patent: May 21, 1996
    Assignee: Intel Corporation
    Inventors: Siva Natarajan, Debendra Mallik
  • Patent number: 5488257
    Abstract: A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of conductive material with the leads of the lead frame.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: January 30, 1996
    Assignee: Intel Corporation
    Inventors: Bidyut Bhattacharyya, Debendra Mallik
  • Patent number: 5444602
    Abstract: An electronic package which has a heat sink that is attached to the lead frame of the package with a material that is both electrically and thermally conductive. The lead frame is also coupled to a first surface of an integrated circuit die with tape automated bonded (TAB) leads. The low thermal resistance of the heat sink increases the thermal performance of the package. The heat sink may also be mounted directly to the die with a conductive material so that the die is electrically grounded to the heat sink. The heat sink is then bonded to the leads of the lead frame that are dedicated to ground. In this embodiment, the heat sink provides the dual functions of a ground plate and a heat spreader.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: August 22, 1995
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Siva Natarajan, Debendra Mallik, Praveen Jain
  • Patent number: 5420461
    Abstract: An integrated circuit device having an array of flexible leads attached to the bottom of an integrated circuit package. There is provided a sheet of electrically conductive material. A plurality of slots are punched into the sheet, such that there is formed a plurality of beams. The beams are then bent into a spring shape. The sheet is placed over an integrated circuit package which has an array of contact pads extending across a bottom surface of the package. The beams are aligned and attached to the contact pads. The beams are then cut and separated from the remainder of the sheet. The sheet is removed, wherein there is constructed an integrated circuit package that has a two dimensional array of flexible leads.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: May 30, 1995
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Bidyut K. Bhattacharyya
  • Patent number: 5369545
    Abstract: A high capacitance/low inductance capacitor module. The module comprises a plurality of conductive power planes that are separated from a plurality of conductive ground planes by layers of dielectric material. The power planes each have opposite extending tabs that are offset from similar tabs extending from the ground planes and which are coupled together by layers of conductive material. Likewise, the tabs of the ground planes are coupled together by additional layers of conductive material. The corresponding power and ground planes are also coupled together by vias located throughout the module. The conductive layers couple both sides of the corresponding conductive planes and provide contact pads for further assembly to a semiconductive die. The module is attached to the semiconductive die by a plurality of gold bumps which are formed on the top surface of the die.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: November 29, 1994
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Debendra Mallik, You Y. Yu
  • Patent number: 5210939
    Abstract: A method for attaching an array of flexible leads to the bottom of an integrated circuit package. There is provided a sheet of electrically conductive material. A plurality of slots are punched into the sheet, such that there is formed a plurality of beams. The beams are then bent into a spring shape. The sheet is placed over an integrated circuit package which has an array of contact pads extending across a bottom surface of the package. The beams are aligned and attached to the contact pads. The beams are then cut and separated from the remainder of the sheet. The sheet is removed, wherein there is constructed an integrated circuit package that has a two dimensional array of flexible leads.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: May 18, 1993
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Bidyut K. Bhattacharyya
  • Patent number: 5098863
    Abstract: A method for packaging integrated circuits for surface mount which provides advantages over prior art techniques by providing increased strength to integrated circuit package leads for increased lead dimensional stability to accommodate the finer pitches needed for high density integrated circuits, i.e., with leadcounts of 200 or more leads. The method is for producing a plastic integrated circuit package that allows for transfer molding using a non-conductive, permanent dambar. The invention includes the resulting leadframe. The method produces a package having embedded leads (on both sides and in between) in a double sided film/adhesive combination which increases lead dimensional stability and which does not require removal before device mounting. The double sided film/adhesive combination is non-conductive, is able to withstand all the package assembly process steps and is applied before a die is dedicated to a leadframe.
    Type: Grant
    Filed: November 29, 1990
    Date of Patent: March 24, 1992
    Assignee: Intel Corporation
    Inventors: Mitch Dolezal, Debendra Mallik, Steve Prough
  • Patent number: 4891687
    Abstract: A multi-layered molded plastic package for encapsulating an integrated circuit is described. The package includes a carrier having a double-layered metal plate which are separated by an adhesive coated insulation tape. A second insulating tape layer is used to bond externally extending leads onto one of the metal plates. Power and ground connections from the terminals of the integrated circuit are made to each of the plates, respectively, as are the power and ground lead connections to the two plates. The power and ground planes remove the requirement for direct physical connection between the power and ground terminals of the integrated circuit and their respective leads.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: January 2, 1990
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Bidyut K. Bhattacharyya
  • Patent number: 4835120
    Abstract: A multi-layered molded plastic package for encapsulating an integrated circuit is described. The package includes a carrier having a double-layered metal plate which are separated by an adhesive coated insulation tape. A second insulating tape layer is used to bond externally extending leads onto one of the metal plates. Power and ground connections from the terminal of the integrated circuit are made to each of the plates, respectively, as are the power and ground lead connections to the two plates. The power and ground planes remove the requirement for direct physical connection between the power and ground terminals of the integrated circuit and their respective leads.
    Type: Grant
    Filed: June 29, 1988
    Date of Patent: May 30, 1989
    Inventors: Debendra Mallik, Bidyut K. Bhattacharyya