Abstract: Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.

Abstract: An assembly including a heat dissipation device having an attachment surface, a substrate having an attachment surface, and a plurality of metal balls extending between the heat dissipation device attachment surface and the substrate attachment surface. The assembly may include at least one microelectronic die disposed between the heat dissipation device attachment surface and the substrate attachment surface.

Abstract: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

Abstract: A semiconductor chip package, an electronic system, and a method of manufacturing such package. A lower structure includes a lower insulating layer and a metal layer made of separate electrical conductors. A wall defines a cavity on the metal layer. Electrical conductors extend from the metal layer to contact points elsewhere in the semiconductor chip package. Conductor members are positioned on the electrical conductors of the metal layer. A semiconductor chip is positioned on the conductor members within the cavity, with an isolation area between the semiconductor chip and the wall. The electrical contacts on the semiconductor chip contact the conductor members to couple the semiconductor chip to the contact points. Underfill material is provided within the isolation area between the perimeter surface and the wall, and is prevented by the wall from spreading to other areas. Placement of the semiconductor chip within the cavity reduces the package thickness.

Abstract: A microelectronic device package including an electrically conductive lid having an attachment surface, a substrate having an attachment surface, at least one interconnect extending between the lid attachment surface and the substrate attachment surface, at least one microelectronic die disposed between the lid attachment surface and the substrate attachment surface, and the substrate having at least one first conductive trace extending between the electrically conductive first interconnect and the microelectronic die. The microelectronic device package allows for the use of the electrically conductive lid as a path for conducting signals (preferably power or ground) to and/or from a microelectronic die.

Abstract: A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

Abstract: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

Abstract: A molded stiffener for a package substrate is presented. The stiffener includes a molded portion. The molded portion is molded of an electrically nonconductive molding compound. A plurality of capacitors are embedded in the molded portion. The capacitors are constructed and arranged to be electrically connected to the package substrate. As such, power delivery performance is improved, and mechanical strength is added to the substrate.

Abstract: An assembly including a heat dissipation device having an attachment surface, a substrate having an attachment surface, and a plurality of metal balls extending between the heat dissipation device attachment surface and the substrate attachment surface. The assembly may include at least one microelectronic die disposed between the heat dissipation device attachment surface and the substrate attachment surface.

Abstract: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One ore more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.

Abstract: A molded stiffener for a package substrate is presented. The stiffener includes a molded portion. The molded portion is molded of an electrically nonconductive molding compound. A plurality of capacitors are embedded in the molded portion. The capacitors are constructed and arranged to be electrically connected to the package substrate. As such, power delivery performance is improved, and mechanical strength is added to the substrate.

Abstract: A molded stiffener for a package substrate is presented. The stiffener includes a molded portion. The molded portion is molded of an electrically nonconductive molding compound. A plurality of capacitors are embedded in the molded portion. The capacitors are constructed and arranged to be electrically connected to the package substrate. As such, power delivery performance is improved, and mechanical strength is added to the substrate.

Abstract: Apparatus and methods are provided to enable circuit configuration of a substrate by the setting of settable bits associated with those circuits. An electrically conductive material is deposited onto selected settable bits which closes the desired circuit between the settable bits. In one embodiment in accordance with the invention, a carrier substrate is provided that comprises settable bits which are used to control a microelectronic package's electrical characteristics. In one embodiment, the settable bits are in the form of sets of spaced-apart bit pads which form an open circuit between a logic circuit and electrical ground (Vss). The open circuit is closed with the application of electrically conductive material that bridges the set of spaced-apart bit pads. The settable bits, therefore, do not require the addition of high profile components such as 0-ohm resisters to form the electrical bridging function between the bit pads of a settable bit.

Abstract: A molded stiffener for a package substrate is presented. The stiffener includes a molded portion. The molded portion is molded of an electrically nonconductive molding compound. A plurality of capacitors are embedded in the molded portion. The capacitors are constructed and arranged to be electrically connected to the package substrate. As such, power delivery performance is improved, and mechanical strength is added to the substrate.

Abstract: A semiconductor chip package, an electronic system, and a method of manufacturing such package. A lower structure includes a lower insulating layer and a metal layer made of separate electrical conductors. A wall defines a cavity on the metal layer. Electrical conductors extend from the metal layer to contact points elsewhere in the semiconductor chip package. Conductor members are positioned on the electrical conductors of the metal layer. A semiconductor chip is positioned on the conductor members within the cavity, with an isolation area between the semiconductor chip and the wall. The electrical contacts on the semiconductor chip contact the conductor members to couple the semiconductor chip to the contact points. Underfill material is provided within the isolation area between the perimeter surface and the wall, and is prevented by the wall from spreading to other areas. Placement of the semiconductor chip within the cavity reduces the package thickness.

Abstract: An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.

Abstract: An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.

Abstract: An integrated circuit package with a two dimensional array of leads that each have a foot portion which is bent at an angle relative to a vertical column portion of the leads. The foot portion of the leads are typically soldered to the surface pads of a printed circuit board. The leads are formed by a tooling apparatus which has a bending device that bends the foot portions of the leads onto a bending die. The tooling apparatus insures that the foot portions of the leads are all coplanar with the printed circuit board.

Abstract: Methods for soldering a ball grid array (BGA) integrated circuit package to a printed circuit board. One method includes the steps of applying a solder flux to the conductive surface pads of a printed circuit board and capturing a plurality of solder balls with a separate fixture. The fixture is then placed onto the printed circuit board and the solder balls are released onto the conductive surface pads. The fixture is removed and an integrated circuit package is placed onto the solder balls. Solder flux may be applied to the bottom of the package to adhere the package to the balls. The solder balls are then reflowed to attach the package to the board. The flux provides a bonding agent which maintains the position of the solder balls and package while the solder is being reflowed. Another method includes the step of placing a fixture adjacent to the integrated circuit package so that a plurality of openings in the fixture are aligned with surface pads located on the bottom surface of the package.

Abstract: A multi-layer integrated circuit package which contains layers of dielectric that substantially reduce metal migration between the metal conductors of the package. The package has metal baseplates that are separated from a lead frame by a plurality of dielectric tapes. The integrated circuit is mounted to the baseplate which has a plurality of tabs that are connected to the lead frame of the package. The power or ground leads of the package are bonded to the corresponding baseplate through the tabs of the metal plate. The lead frame, metal baseplate and dielectric tapes all have center openings to provide clearance for the integrated circuit. The center opening of the tapes are such that the dielectric material extends beyond the ends of the baseplates and lead frame.