Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Abstract: A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.

Abstract: A method of making a magnetic random access memory (MRAM) device comprising forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a first reference layer, a free layer, and a first tunnel barrier layer; and depositing an encapsulating silicon nitride film on and along sidewalls of the magnetic tunnel junction; wherein the silicon nitride film has a N:Si ratio from 0.1 to 1. An MRAM device made by the above method is also disclosed.

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract: A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors.

Abstract: A method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating. The inorganic antireflective coating is vapor deposited and contains atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. At least one interconnect pattern is then formed within the at least one patternable low-k material. Next, the at least one patternable low-k material containing the at least one interconnect pattern is cured.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Abstract: A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors.

Abstract: A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors.

Abstract: A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors.

Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Abstract: Techniques and structures for laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation. A structure includes a crystalline semiconductor having at least one surface, a doped crystalline region disposed in at least one selected area of the semiconductor surface, and a dopant-containing amorphous silicon layer stack containing a same dopant as present in the doped crystalline region on at least a portion of the semiconductor surface outside the selected area, wherein the dopant-containing amorphous silicon layer stack passivates the portion of the semiconductor surface on which it is disposed.

Abstract: Techniques and structures for laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation are provided. An example method includes forming a dopant-containing amorphous silicon layer stack on at least one portion of a surface of a crystalline semiconductor layer; and irradiating a selected area of the dopant-containing amorphous silicon layer stack, wherein the selected area of the dopant-containing amorphous silicon layer stack interacts with an upper portion of the underlying crystalline semiconductor layer to form a doped, conductive crystalline region, and each non-selected area of the dopant-containing amorphous silicon layer stack remains intact on the at least one portion of the surface of the crystalline semiconductor layer.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.