Abstract: Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of coating material exhibits a coating layer Vickers hardness value. Systems and components include where the coating layer Vickers hardness value is greater than or about 10% less than the component Vickers hardness value.

Abstract: Exemplary methods of forming a silicon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber and include one or more features. The methods may include generating plasma effluents of the silicon-containing precursor in the processing region. The methods may include depositing a silicon-containing material on a vertically extending portion and a horizontally extending portion of the feature. Methods include soaking the deposited silicon-containing material with a second silicon-containing material.

Abstract: Substrate support assemblies may include an electrostatic chuck body defining a substrate support surface that defines a substrate seat. Assemblies may include a support stem coupled with the electrostatic chuck body. Assemblies may include a first bipolar electrode embedded within the electrostatic chuck body. Assemblies may include a second bipolar electrode embedded within the electrostatic chuck body radially inward of at least a portion of the first bipolar electrode and coaxial with the first bipolar electrode. Assemblies may include an annular electrode disposed about the first bipolar electrode, where the annular electrode is DC floated and RF powered and exhibits an induced DC current.

Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.

Abstract: Exemplary semiconductor structures may include a stack of layers overlying a substrate. The stack of layers may include a first portion of layers, a second portion of layers overlying the first portion of layers, and a third portion of layers overlying the second portion of layers. The first portion of layers, the second portion of layers, and the third portion of layers may include alternating layers of a silicon oxide material and a silicon nitride material. One or more apertures may be formed through the stack of layers. A lateral notch in each individual layer of silicon nitride material at an interface of the individual layer of silicon nitride material and an overlying layer of silicon oxide material may extend a distance less than or about 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material.

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support within the chamber body. The substrate support may define a substrate support surface. The chambers may include a faceplate supported atop the chamber body. The substrate support and a bottom surface of the faceplate may at least partially define a processing region. The bottom surface of the faceplate may define an annular protrusion that is directly above at least a portion of a radially outer 10% of the substrate support surface and an annular groove that is positioned radially outward of the annular protrusion. At least a portion of the annular groove may extend radially outward beyond the substrate support surface. The faceplate may define apertures through the faceplate. A first subset of the apertures may extend through the annular protrusion and a second subset of the apertures may extend through the annular groove.

Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency above 15 MHz. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.0.

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: A method includes obtaining, by a processing device, first data indicative of overlay error of a substrate. The method further includes generating second data indicative of first stress uniformity of the substrate based on the first data. The method further includes performing a corrective action based on the second data.

Abstract: Exemplary processing methods may include i) providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include one or more features defining one or more sidewalls. The methods may include ii) forming plasma effluents of the one or more deposition precursors. The methods may include iii) contacting the substrate with the plasma effluents of the one or more deposition precursors. The contacting may deposit a doped silicon-and-oxygen-containing material on the substrate. A first portion of the doped silicon-and-oxygen-containing material deposited on the one or more sidewalls of the one or more features may be characterized by a poorer film quality than a second portion of the doped silicon-and-oxygen-containing material deposited on a lower portion of the one or more features.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon nitride on a semiconductor substrate. The layer of silicon nitride may be characterized by a first roughness. The methods may include performing a post-deposition treatment on the layer of silicon nitride. The methods may include reducing a roughness of the layer of silicon nitride such that the layer of silicon nitride may be characterized by a second roughness less than the first roughness.

Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor to the processing region. The methods may include generating plasma effluents of the silicon-containing precursor and plasma effluents of the hydrogen-containing precursor in the processing region. The plasma effluents may be generated at a frequency greater than 15 MHz. The methods may include depositing a silicon-containing material on the substrate.

Abstract: Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The deposition precursors may include a silicon-containing precursor. The methods may include providing a dopant precursor to the processing region of the semiconductor processing chamber. The dopant precursor may include a phosphorous-containing precursor. The methods may include generating plasma effluents of the deposition precursors and the dopant precursor. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of greater than or about ?50 MPa.

Abstract: Capacitor devices containing silicon boron nitride with high boron concentration are provided. In one or more examples, a capacitor device is provided and contains a stopper layer containing silicon boron nitride and disposed on a substrate, a dielectric layer disposed on the stopper layer, vias formed within the dielectric layer and the stopper layer, metal contacts disposed on bottoms of the vias, a nitride barrier layer containing a metal nitride material and disposed on walls of the vias and disposed on the metal contacts, and an oxide layer disposed within the vias on the nitride barrier layer, wherein the oxide layer contains one or more holes or voids formed therein. The silicon boron nitride contains about 18 atomic percent (at %) to about 50 at % of boron.

Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first data set reflecting distortions associated with a substrate and generating a second data set reflecting reduced noise in the distortions of the first data set. A third data set is generated by projecting a plurality of direction components associated with the second data set to a radial direction and a stress or strain map is generated indicating at least one of stress or strain exhibited by the substrate by determining a magnitude associated with a subset of the third data set.

Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate and on one or more components of the semiconductor processing chamber. The methods may include providing a fluorine-containing precursor to the processing region. The fluorine-containing precursor may be plasma-free when provided to the processing region. The methods may include contacting the silicon-containing material on the one or more components of the semiconductor processing chamber with the fluorine-containing precursor. The methods may include removing at least a portion of the silicon-containing material on the one or more components of the semiconductor processing chamber with the fluorine-containing precursor.

Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.

Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.