Patents by Inventor Deepak C. Sekar

Deepak C. Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273121
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.
    Type: Application
    Filed: May 11, 2019
    Publication date: September 5, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 10388863
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 20, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10388568
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 20, 2019
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10354995
    Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the dev
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 16, 2019
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Zeev Wurman
  • Patent number: 10325651
    Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.
    Type: Grant
    Filed: April 23, 2017
    Date of Patent: June 18, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190164834
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells includes one first transistor, where each of the second memory cells includes one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, and where the forming at least one third level includes forming a window within the third level so to allow a lithography alignment through the third level to an alignment mark disposed und
    Type: Application
    Filed: January 11, 2019
    Publication date: May 30, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190148234
    Abstract: A method for producing a 3D memory device including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form memory cells within the second level and within the third level, each of the first memory cells include one first transistor, each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, the memory is NAND, the first level includes memory peripheral circuits, at least one of the first memory cells is at least partially atop a portion of the peripheral circuits.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10290682
    Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 14, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Publication number: 20190139827
    Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where the contact plugs are connected to the plurality of first single crystal transistors and the first metal layer, where the first metal layer interconnect the first single crystal transistors forming memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a second metal layer; a third metal layer, where the second metal layer overlays the third level, where the third metal layer overlays the second metal layer, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, where the memory control circuits include control sub-circuits to remap a degraded memory block to an alternative memory space within th
    Type: Application
    Filed: October 22, 2018
    Publication date: May 9, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190109049
    Abstract: A 3D semiconductor device including: a first level comprising first single crystal transistors, a first metal layer, and a plurality of latches; a second level comprising a plurality of second transistors, wherein said second level comprises first memory cells, and wherein said first memory cells each comprise at least one of said plurality of second transistors; a third level comprising a plurality of third transistors, wherein said third level comprises second memory cells, wherein said second memory cells each comprise at least one of said plurality of third transistors, wherein said second level overlays said first level, and wherein said third level overlays said second level; a second metal layer overlaying said third level, said second metal layer comprising a plurality of bit-lines, wherein said plurality of second transistors are aligned to said first single crystal transistors with less than 100 nm alignment error, wherein said plurality of second transistors are junction-less transistors, and where
    Type: Application
    Filed: November 5, 2018
    Publication date: April 11, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190074371
    Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a first silicon channel; a second layer including second transistors each including a second silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer overlying the second transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistors are junction-less transistors.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190074222
    Abstract: A 3D semiconductor device including: a first level including first single crystal transistors and a first metal layer; a second level including a plurality of second transistors; where the second level includes memory cells including the plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level; and vertically oriented conductive plugs, the vertically oriented conductive plugs connect from the second transistors to the first metal layer, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, and where one end of at least one of the vertically oriented conductive plugs functions also as a contact to a portion of each of the plurality of second transistors.
    Type: Application
    Filed: November 3, 2018
    Publication date: March 7, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190067109
    Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the plurality of first single crystal transistors to the first metal layer, and where connections include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, the third level overlays the second level; a second metal layer overlaying the third level; and a third metal layer overlaying the second metal layer, where second transistors are aligned to first transistors with less than 40 nm alignment error, where the second level includes first memory cells, where the third level includes second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.
    Type: Application
    Filed: October 24, 2018
    Publication date: February 28, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190067110
    Abstract: A 3D semiconductor device including: a first level with first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the first transistors to the first metal, where connections formed logic circuits; a second level with second transistors; a third level with third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level, second level includes first memory cells where each of the memory cells include at least one of the second transistors; and vertically oriented conductive plugs, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, where one end of each of the vertically oriented conductive plugs are connected to the second metal layer, where at least one of the vertically oriented conductive plugs is disposed directly on one
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10217667
    Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: February 26, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Publication number: 20190057903
    Abstract: A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190027409
    Abstract: A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed follow
    Type: Application
    Filed: September 12, 2018
    Publication date: January 24, 2019
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190006240
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel.
    Type: Application
    Filed: August 11, 2018
    Publication date: January 3, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20190006222
    Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.
    Type: Application
    Filed: August 12, 2018
    Publication date: January 3, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman
  • Patent number: 10157909
    Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 18, 2018
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist