Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via has a diameter of less than 400 nm and greater than 5 nm.

Abstract: A method for producing a 3D semiconductor device, the method comprising: providing a first level, said first level comprising a first single crystal layer; forming first alignment marks and control circuits in and/or on said first level, wherein said control circuits comprise first single crystal transistors, and wherein said control circuits comprise at least two interconnection metal layers; forming at least one second level disposed on top of said control circuits; performing a first etch step into said second level; and performing additional processing steps to form a plurality of first memory cells within said second level, wherein each of said memory cells comprise at least one second transistors, and wherein said additional processing steps comprise depositing a gate electrode for said second transistors.

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer and plurality of first transistors; a first metal layer including interconnects between first transistors, where the interconnects between the first transistors includes forming logic gates; a second metal layer atop at least a portion of the first metal layer, second transistors which are vertically oriented, are also atop a portion of the second metal layer; where at least eight of the first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the second transistors is at least partially directly atop of the NAND logic structure; and a third metal layer atop at least a portion of the second transistors, where the second metal layer is aligned to the first metal layer with a less than 150 nm misalignment.

Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed on top of the control circuits; performing a first etch step including etching first holes within the second level; and performing additional processing steps (including Atomic Layer Deposition) to form a plurality of memory cells within the second level, where each memory cell includes at least one second transistor, where making the second level includes forming lithography holes atop of the first alignment marks which enables performing lithography steps aligned to the first alignment marks, including at least the first etch step above.

Abstract: A 3D semiconductor device including: a first single-crystal layer including a plurality of first transistors; at least one first metal layer disposed atop the plurality of first transistors; a second metal layer disposed atop the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed atop the plurality of fourth transistors; a fourth metal layer disposed atop the third metal layer; a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer disposed above the plurality of first transistors; a second metal layer disposed above the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed above the plurality of fourth transistors; a fourth metal layer disposed above the third metal layer; and a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where the device includes an array of memory cells, and where at least one of the memory cells includes one of the plurality of third transistors.

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes at least one LED driving circuit; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer, where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes at least one LED driving circuit; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer, where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first single crystal transistors; a first metal layer; a second metal layer disposed atop the first metal layer; second transistors disposed atop of the second metal layer; third transistors disposed atop of the second transistors, where at least one of the third transistors includes at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate, and where a distance from at least one of the third transistors to at least one of the second transistors is less than 1 micron.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least two metal layers; a plurality of logic gates including the at least two metal layers interconnecting the plurality of first transistors; a plurality of second transistors disposed atop the at least two metal layers; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least two rows by two columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, and where at least one of the second transistors include a metal gate.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.

Abstract: A method for producing a 3D memory device, including: providing a first level including a single crystal layer and control circuits, the control circuits include a plurality of first single crystal transistors; forming at least one second level disposed above the first level; processing to form a plurality of second transistors, where the processing includes forming a plurality of memory cells, each of the plurality of memory cells includes at least one of the plurality of second transistors, where the control circuits control the plurality of memory cells, where at least one of the plurality of memory cells is at least partially atop a portion of the control circuits, where processing the control circuits accounts for a thermal budget associated with processing of the second transistors by adjusting annealing of the first transistors accordingly; processing to replace gate material of at least one of the plurality of second transistors.