Patents by Inventor Deepak D. Sherlekar
Deepak D. Sherlekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230274064Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Inventors: Deepak D. SHERLEKAR, Basannagouda REDDY, Shanie GEORGE
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Patent number: 11681848Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.Type: GrantFiled: May 12, 2021Date of Patent: June 20, 2023Assignee: Synopsys, Inc.Inventors: Deepak D. Sherlekar, Basannagouda Reddy, Shanie George
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Publication number: 20210357567Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.Type: ApplicationFiled: May 12, 2021Publication date: November 18, 2021Inventors: Deepak D. SHERLEKAR, Basannagouda REDDY, Shanie GEORGE
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Patent number: 10990722Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.Type: GrantFiled: June 1, 2015Date of Patent: April 27, 2021Assignee: SYNOPSYS, INC.Inventors: Jamil Kawa, Victor Moroz, Deepak D. Sherlekar
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Patent number: 10205440Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.Type: GrantFiled: November 29, 2017Date of Patent: February 12, 2019Assignee: Synopsys, Inc.Inventors: Basannagouda Somanath Reddy, Deepak D. Sherlekar, Princy K. Varghese
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Publication number: 20180159513Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.Type: ApplicationFiled: November 29, 2017Publication date: June 7, 2018Inventors: Basannagouda Somanath Reddy, Deepak D. Sherlekar, Princy K. Varghese
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Patent number: 9691764Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.Type: GrantFiled: October 26, 2015Date of Patent: June 27, 2017Assignee: SYNOPSYS, INC.Inventors: Jamil Kawa, Victor Moroz, Deepak D. Sherlekar
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Publication number: 20160043083Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.Type: ApplicationFiled: October 26, 2015Publication date: February 11, 2016Applicant: SYNOPSYS, INC.Inventors: JAMIL KAWA, VICTOR MOROZ, DEEPAK D. SHERLEKAR
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Patent number: 9257429Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.Type: GrantFiled: March 23, 2015Date of Patent: February 9, 2016Assignee: Synopsys, Inc.Inventors: Victor Moroz, Deepak D. Sherlekar
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Publication number: 20150303196Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Applicant: SYNOPSYS, INC.Inventors: JAMIL KAWA, VICTOR MOROZ, DEEPAK D. SHERLEKAR
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Publication number: 20150261894Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Applicant: SYNOPSYS, INC.Inventors: Jamil KAWA, Victor MOROZ, Deepak D. SHERLEKAR
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Publication number: 20150194429Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Applicant: SYNOPSYS, INC.Inventors: Victor Moroz, Deepak D. Sherlekar
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Patent number: 9076673Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.Type: GrantFiled: December 15, 2014Date of Patent: July 7, 2015Assignee: SYNOPSYS, INC.Inventors: Jamil Kawa, Victor Moroz, Deepak D. Sherlekar
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Patent number: 9048121Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.Type: GrantFiled: October 10, 2013Date of Patent: June 2, 2015Assignee: SYNOPSYS, INC.Inventors: Jamil Kawa, Victor Moroz, Deepak D. Sherlekar
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Publication number: 20150137256Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.Type: ApplicationFiled: December 15, 2014Publication date: May 21, 2015Applicant: SYNOPSYS, INC.Inventors: JAMIL KAWA, VICTOR MOROZ, DEEPAK D. SHERLEKAR
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Patent number: 8987828Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.Type: GrantFiled: April 14, 2014Date of Patent: March 24, 2015Assignee: Synopsys, Inc.Inventors: Victor Moroz, Deepak D. Sherlekar
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Patent number: 8941150Abstract: An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules.Type: GrantFiled: April 22, 2014Date of Patent: January 27, 2015Assignee: Synopsys, Inc.Inventors: Deepak D. Sherlekar, Vahe Hovsepyan
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Patent number: 8924908Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.Type: GrantFiled: October 29, 2013Date of Patent: December 30, 2014Assignee: Synopsys, Inc.Inventors: Jamil Kawa, Victor Moroz, Deepak D. Sherlekar
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Publication number: 20140229908Abstract: An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules.Type: ApplicationFiled: April 22, 2014Publication date: August 14, 2014Applicant: SYNOPSYS, INC.Inventors: Deepak D. Sherlekar, Vahe Hovsepyan
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Publication number: 20140217514Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.Type: ApplicationFiled: April 14, 2014Publication date: August 7, 2014Applicant: Synopsys, Inc.Inventors: Victor Moroz, Deepak D. Sherlekar