Patents by Inventor Deepak Goyal
Deepak Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12294470Abstract: A fabric control protocol (FCP) and packet forwarding mechanisms are described that maximize utilization of bandwidth within massive, large-scale data centers having multi-stage data center switch fabric topologies, such as topologies that include a third switching layer formed by super spine switches. Automatic generation of data plane forwarding information referred to as FCP path information enumerates, for each data processing unit (DPU), the available FCP paths. The FCP path information may be based on unique combinations of peak points of the switch fabric for a given DPU with FCP colors assigned to network links that are used to multi-home the DPU to the switch fabric.Type: GrantFiled: June 24, 2021Date of Patent: May 6, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Yixing Ruan, Deepak Goel, Narendra Jayawant Gathoo, Philip A. Thomas, Srihari Raju Vegesna, Pradeep Sindhu, Wael Noureddine, Robert William Bowdidge, Ayaskant Pani, Gopesh Goyal
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Patent number: 12276985Abstract: An obstruction avoidance system may include a agronomy vehicle, at least one sensor configured to output signals serving as a basis for a three-dimensional (3D) point cloud and to output signals corresponding to a two-dimensional (2D) image, and instructions to direct a processor to capture a particular 2D image and to obtain signals serving as a basis for a particular 3D point cloud; identify an obstruction candidate in the particular 2d image; correlate the obstruction candidate to a portion of the particular 3D point cloud to determine a value for a parameter of the obstruction candidate; classify the obstruction candidate as an obstruction based upon the parameter; and output control signals to alter a state of the agronomy vehicle in response to the obstruction candidate being classified as an obstruction.Type: GrantFiled: September 30, 2021Date of Patent: April 15, 2025Assignee: Zimeno Inc.Inventors: Deepak Rajasekhar Karishetti, Sanket Goyal
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Patent number: 12271742Abstract: Implementations relate to determining a rendering type for an application that is executing automatically. Based on user interactions with an application that is associated with specified input from the user while the user is interacting with the application, a confidence metric is generated for each specified input and a rendering type is determined based on the confidence metrics. Subsequently, when the user requests that a sequence of actions be performed, the application will be displayed according to the rendering type.Type: GrantFiled: August 4, 2023Date of Patent: April 8, 2025Assignee: GOOGLE LLCInventors: Cliff Kuang, Diana Avram, Mugurel-Ionut Andreica, Radu Voroneanu, Sneha Ashok, Deepak Goyal, Kyunghoon Lee, Alice Liang, Dana Ritter, Adam Coimbra, Anton Berezin, Andre Elisseeff
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Patent number: 12261926Abstract: A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).Type: GrantFiled: November 12, 2021Date of Patent: March 25, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Deepak Goel, Narendra Jayawant Gathoo, Philip A. Thomas, Srihari Raju Vegesna, Pradeep Sindhu, Wael Noureddine, Robert William Bowdidge, Ayaskant Pani, Gopesh Goyal
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Patent number: 12241375Abstract: A turbine engine is provided. The turbine engine defines an axial direction and a radial direction, and includes: a rotor; a stator comprising a carrier; a seal assembly disposed between the rotor and the stator, the seal assembly defining a high-pressure side and a low-pressure side and comprising a plurality of seal segments, the plurality of seal segments including a seal segment having a seal face forming a fluid bearing with the rotor, a lip, and a body, the lip extending from the body along the axial direction of the turbine engine on the high-pressure side and including an outer pressurization surface along the radial direction of the turbine engine; and a seal support assembly, the seal support assembly comprising a spring arrangement extending between the carrier and the first seal segment to counter a pressure on the outer pressurization surface during operation of the turbine engine.Type: GrantFiled: March 24, 2023Date of Patent: March 4, 2025Assignee: General Electric CompanyInventors: Ravindra Shankar Ganiger, David Raju Yamarthi, Chandrashekhar Kandukuri, Deepak Trivedi, Narendra Anand Hardikar, Vidyashankar Ramasastry Buravalla, Steven Douglas Johnson, Amit Goyal, Grant Robert Portune, Himanshu Gupta, Srinivasan Swaminathan, Shalini Thimmegowda, Guru Venkata Dattu Jonnalagadda, Shalabh Saxena, Prateek Jalan
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Publication number: 20250068743Abstract: The systems and methods disclosed herein receives artifacts generated using a first set of models within a multi-model superstructure. The multi-model superstructure includes a second set of models to test the first set of models. The multi-model superstructure dynamically routes the artifacts of the first set of models to one or more models of the second set of models by (i) determining a set of dimensions of the artifacts against which to evaluate the artifacts and (ii) identifying the models in the second set used to test the particular dimension. The second set of models then assesses each artifact against a set of assessment metrics. If an artifact fails to meet one or more assessment metrics, the second set of models generates actions to align the artifact with the set of assessment metrics.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Inventors: Sofia RAHMAN, David GRIFFITHS, James MYERS, Prashant PRAVEEN, Shardul MALVIYA, Wayne LIAO, Deepak JAIN, Samantha CORY, Mariusz SATERNUS, Daniel LEWANDOWSKI, Biraj Krushna RATH, Stuart MURRAY, Philip DAVIES, Payal JAIN, Tariq Husayn MAONAH, Vishal MYSORE, Ramkumar AYYADURAI, Chamindra DESILVA, William Franklin Cameron, Miriam Silver, Prithvi Narayana Rao, Pramod Goyal, Manjit Rajaretnam
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Patent number: 12231353Abstract: A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).Type: GrantFiled: January 28, 2020Date of Patent: February 18, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Deepak Goel, Narendra Jayawant Gathoo, Philip A Thomas, Srihari Raju Vegesna, Pradeep Sindhu, Wael Noureddine, Robert William Bowdidge, Ayaskant Pani, Gopesh Goyal
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Publication number: 20250045071Abstract: Implementations relate to determining a rendering type for an application that is executing automatically. Based on user interactions with an application that is associated with specified input from the user while the user is interacting with the application, a confidence metric is generated for each specified input and a rendering type is determined based on the confidence metrics. Subsequently, when the user requests that a sequence of actions be performed, the application will be displayed according to the rendering type.Type: ApplicationFiled: August 4, 2023Publication date: February 6, 2025Inventors: Cliff Kuang, Diana Avram, Mugurel-Ionut Andreica, Radu Voroneanu, Sneha Ashok, Deepak Goyal, Kyunghoon Lee, Alice Liang, Dana Ritter, Adam Coimbra, Anton Berezin, Andre Elisseeff
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Publication number: 20250013438Abstract: A method include receiving a natural language prompt from a user comprising a command to generate a code script for an automated assistant to perform a routine. The routine includes multiple discrete actions specified by the natural language prompt. The method further includes processing, by a pre-trained large language model (LLM), the natural language prompt to generate the code script as an LLM output, and processing the code script to determine the code script is incomplete, thereby rendering the code script unsuitable for the automated assistant to fulfill performance of the routine. Based on determining the code script is incomplete, the method includes issuing a user prompt soliciting the user to provide additional information needed to complete the code script and receiving user input of the additional information needed to complete the code script. The method includes supplementing the code script with the additional information to render completed code script.Type: ApplicationFiled: June 18, 2024Publication date: January 9, 2025Applicant: Google LLCInventors: Michael Andrew Goodman, Deepak Goyal
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Patent number: 12094800Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.Type: GrantFiled: December 19, 2019Date of Patent: September 17, 2024Assignee: Intel CorporationInventors: Zhimin Wan, Jin Yang, Chia-Pin Chiu, Peng Li, Deepak Goyal
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Patent number: 11798861Abstract: Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.Type: GrantFiled: July 8, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Peng Li, Kelly P. Lofgreen, Manish Dubey, Bamidele Daniel Falola, Ken Hackenberg, Shenavia S. Howell, Sergio Antonio Chan Arguedas, Yongmei Liu, Deepak Goyal
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Patent number: 11791237Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the second surface of the package substrate; a cooling apparatus thermally coupled to the second surface of the die; and a thermal interface material (TIM) between the second surface of the die and the cooling apparatus, wherein the TIM includes an indium alloy having a liquidus temperature equal to or greater than about 245 degrees Celsius.Type: GrantFiled: June 27, 2018Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Peng Li, Sergio Antonio Chan Arguedas, Yongmei Liu, Deepak Goyal, Ken Hackenberg
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Patent number: 11551956Abstract: According to the various examples, a fully integrated system and method for failure analysis using RF-based thermometry enable the detection and location of defects and failures in complex semiconductor packaging architectures. The system provides synchronous amplified RF signals to generate unique thermal signatures at defect locations based on dielectric relaxation loss and heating.Type: GrantFiled: June 25, 2020Date of Patent: January 10, 2023Assignee: INTEL CORPORATIONInventors: Chandrashekara Shashank Kaira, Phillip C. Miller, Purushotham Kaushik Muthur Srinath, Deepak Goyal
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Patent number: 11506709Abstract: Embodiments may relate an x-ray filter. The x-ray filter may be configured to be positioned between an x-ray source output and a device under test (DUT) that is to be x-rayed. The x-ray filter may include at least 80% titanium (Ti) by weight. Other embodiments may be described or claimed.Type: GrantFiled: November 23, 2018Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Mario Pacheco, Deepak Goyal
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Patent number: 11476120Abstract: Systems and methods of sample preparation using dual ion beam trenching are described. In an example, an inside of a semiconductor package is non-destructively imaged to determine a region of interest (ROI). A mask is positioned over the semiconductor package, and a mask window is aligned with the ROI. A first ion beam and a second ion beam are swept, simultaneously or sequentially, along an edge of the mask window to trench the semiconductor package and to expose the ROI for analysis.Type: GrantFiled: March 30, 2017Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Purushotham Kaushik Muthur Srinath, Richard Kenneth Brewer, Deepak Goyal
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Publication number: 20220199482Abstract: Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: Chia-Pin CHIU, Zhimin WAN, Peng LI, Deepak GOYAL
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Patent number: 11346818Abstract: According to various examples, a method for non-destructive detection of defects in a semiconductor die is described. The method may include positioning an emitter above the semiconductor die. The method may include generating an emitted wave using the emitter that is directed to a focal point on a surface of the die. The method may include generating a reflected wave from the focal point. The focal point may act as a point source reflecting the emitted wave. The method may include positioning a receiver above the die to receive the reflected wave. The method may also include measuring the reflected wave to detect modulations in amplitude in the reflected wave.Type: GrantFiled: May 22, 2020Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Mario Pacheco, Odissei Touzanov, Jacob Woolsey, Deepak Goyal
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Patent number: 11281657Abstract: A distributed system including multiple processing nodes. The distributed system can perform certain acts. The acts can include receiving a first conflation event identifying a first node and a second node. The first node can be part of a first set. The first set can include a sole parent node stored at a first processing node of the multiple processing nodes. The second node can be part of a second set. The second set can include a sole parent node stored at a second processing node of the multiple processing nodes. The first and second sets can be disjoint sets. The first conflation event can be received at an event-driven stream application at one of the multiple processing nodes. The acts also can include conflating the first set and the second set into a conflated set. The conflated set can include the first and second nodes. The conflated set can include a sole parent node.Type: GrantFiled: January 30, 2020Date of Patent: March 22, 2022Assignee: WALMART APOLLO, LLCInventors: Deepak Goyal, Giridhar Addepalli, Sebastien Jean-Maurice Olivier Pehu, Saigopal Thota, Mridul Jain, Navinder Pal Singh Brar
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Patent number: 11226353Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.Type: GrantFiled: March 31, 2017Date of Patent: January 18, 2022Assignee: Intel CorporationInventors: Chengqing Hu, Mayue Xie, Simranjit S. Khalsa, Deepak Goyal
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Publication number: 20210407833Abstract: According to the various examples, a fully integrated system and method for failure analysis using RF-based thermometry enable the detection and location of defects and failures in complex semiconductor packaging architectures. The system provides synchronous amplified RF signals to generate unique thermal signatures at defect locations based on dielectric relaxation loss and heating.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Chandrashekara Shashank Kaira, Phillip C. Miller, Purushotham Kaushik Muthur Srinath, Deepak Goyal