Patents by Inventor Deepak Goyal

Deepak Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9746428
    Abstract: Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line monitoring of both resist footing defects and conductive trace undercut defects. The defects may be detected at the interface between dry film resist (DFR) footings and conductive trace footing found on insulating layer top surfaces of a packaging substrate. Such footing and undercut defects may other wise be considered “hidden defects”. Using the WLI microscope with a tilted objective lens provides a high-throughput and low cost metrology and tool for non-destructive, non-contact, in-line monitoring.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Shuhong Liu, Zhiyong Wang, Nilanjan Z. Ghosh, Deepak Goyal
  • Publication number: 20170176173
    Abstract: Described herein are devices and techniques for measuring a thickness of a surface layer. A device can include a detector, a processor, and a memory. The detector can be arranged to receive reflected light from a surface of a sample. The processor can be in electrical communication with the detector. The memory can store instructions that, when executed by the processor, can cause the processor to perform operations. The operations can include receiving optical data from the detector, determining a polarization change of the reflected light, the polarization change being a function of the optical data, and determining a thickness of the surface layer using the polarization change and the wavelength of the incident light. The optical data can include information regarding the phase difference of the reflected light and the incident light. Also described are other embodiments.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Yanmei Song, Yongmei Liu, Deepak Goyal, Donglai David Lu, Marcel A. Wall
  • Publication number: 20170170080
    Abstract: A material thickness adjustment device and associated methods are shown. Material thickness adjustment devices and methods shown include eddy current measurement to determine material thickness during a deposition or removal operation. Feedback from the measured thickness may then be applied to adjust one or more processing parameters to meet a desired thickness.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Applicant: Intel Corporation
    Inventors: Darko Grujicic, Nilanjan Ghosh, Marcel A. Wall, Deepak Goyal
  • Patent number: 9625256
    Abstract: Techniques and mechanisms for evaluating misalignment of circuit structures. In an embodiment, infrared (IR) radiation is variously focused on different planes of an assembly including an integrated circuit (IC) chip and a substrate that is to be coupled to, or that is coupled to, the IC chip. The cross-sectional planes include respective structures that variously reflect IR radiation. The reflected IR radiation is measured to create images each representing a corresponding cross-section of the assembly. In another embodiment, respective reference features of the images are identified and evaluated to determine whether a misalignment between the reference features satisfies one or more threshold test conditions.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Purushotham Kaushik Muthur Srinath, Mario Pacheco, Deepak Goyal
  • Publication number: 20170089951
    Abstract: An apparatus comprises a contactless sense probe, an electro optic sensor module, and a test signal emitter circuit. The contactless sense probe includes a photoconductive switch and the signal bandwidth of the photoconductive switch is variable. The test signal emitter circuit configured to apply a test signal to a device under test (DUT) at a first location of the DUT, wherein the test signal includes a test signal frequency. The electro-optic sensor module is coupled to the contactless sense probe and configured to: generate an impulse signal at the contactless sense probe using an optical signal input to the first photoconductive switch; sense the test signal frequency in the impulse signal using the contactless sense probe at a second location of the DUT; and generate an indication of a defect in the DUT when the test signal frequency is undetected in the impulse signal.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Mayue Xie, Hemachandar Tanukonda Devarajulu, Deepak Goyal
  • Patent number: 9508610
    Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Shuhong Liu, Nilanjan Z. Ghosh, Zhiyong Wang, Deepak Goyal, Shripad Gokhale, Jieping Zhang
  • Publication number: 20160274044
    Abstract: Circuit device inspection system using temperature gradients. In some embodiments, a system may include an infrared camera, first and second temperature sources, controller circuitry to cause the infrared camera to capture an infrared image of a region of a circuit device and to cause the first and second temperature sources to generate first and second temperature outputs to be applied to first and second locations on the circuit device, and processing circuitry to generate temperature gradient data. The temperature gradient data may be indicative of discontinuities in traces in the circuit device.
    Type: Application
    Filed: March 20, 2015
    Publication date: September 22, 2016
    Inventors: Mayue Xie, Deepak Goyal, Thomas J. Begala
  • Publication number: 20160245758
    Abstract: Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line monitoring of both resist footing defects and conductive trace undercut defects. The defects may be detected at the interface between dry film resist (DFR) footings and conductive trace footing found on insulating layer top surfaces of a packaging substrate. Such footing and undercut defects may other wise be considered “hidden defects”. Using the WLI microscope with a tilted objective lens provides a high-throughput and low cost metrology and tool for non-destructive, non-contact, in-line monitoring.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Shuhong Liu, Zhiyong Wang, Nilanjan Z. Ghosh, Deepak Goyal
  • Patent number: 9389064
    Abstract: Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line monitoring of both resist footing defects and conductive trace undercut defects. The defects may be detected at the interface between dry film resist (DFR) footings and conductive trace footing formed on insulating layer top surfaces of a packaging substrate. Such footing and undercut defects may other wise be considered “hidden defects”. Using the WLI microscope with a tilted objective lens provides a high-throughput and low cost metrology and tool for non-destructive, non-contact, in-line monitoring.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Shuhong Liu, Zhiyong Wang, Nilanjan Ghosh, Deepak Goyal
  • Publication number: 20160093540
    Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.
    Type: Application
    Filed: September 27, 2014
    Publication date: March 31, 2016
    Inventors: Shuhong LIU, Nilanjan Z. GHOSH, Zhiyong WANG, Deepak GOYAL, Shripad GOKHALE, Jieping ZHANG
  • Patent number: 9291576
    Abstract: Generally discussed herein are systems, apparatuses, and methods that can detect a defect in a die. According to an example, a method can include transmitting a first beam of light with a wavelength and optical power configured to produce a reflected beam with at least one milli-Watt of power, linearly polarizing the first beam of light in a specific direction, circularly polarizing the linearly polarized light by a quarter wavelength to create circularly polarized light, directing the circularly polarized light to a device under test, linearly polarizing light reflected off the device under test by a quarter wavelength, or creating an image of the linearly polarized light reflected off the device under test.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Mario Pacheco, Deepak Goyal
  • Publication number: 20160011122
    Abstract: Generally discussed herein are systems, apparatuses, and methods that can detect a defect in a die. According to an example, a method can include transmitting a first beam of light with a wavelength and optical power configured to produce a reflected beam with at least one milli-Watt of power, linearly polarizing the first beam of light in a specific direction, circularly polarizing the linearly polarized light by a quarter wavelength to create circularly polarized light, directing the circularly polarized light to a device under test, linearly polarizing light reflected off the device under test by a quarter wavelength, or creating an image of the linearly polarized light reflected off the device under test.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 14, 2016
    Inventors: Mario Pacheco, Deepak Goyal
  • Publication number: 20150276480
    Abstract: Embodiments include devices, systems and processes for using a combined confocal Raman microscope for inspecting a photo resist film material layer formed on the top surface of a layer of a substrate package, to detect border defects between regions of light exposed (e.g., cured) and unexposed (e.g., uncured) resist film material. Use of the confocal Raman microscope may provide a 3D photo-resist chemical imaging and characterization technique based on combining (1) Raman spectroscopy to identify the borders between regions of light exposed and unexposed resist along XY planes, with (2) Confocal imaging to select a Z-height of the XY planes scanned. Such detection provides fast, high resolution, non-destructive in-line inspection, and improves technical development of polymerization profiles of the resist film material.
    Type: Application
    Filed: March 29, 2014
    Publication date: October 1, 2015
    Inventors: Nilanjan GHOSH, Kevin T. MCCARTHY, Zhiyong WANG, Deepak GOYAL, Changhua LIU, Leonel R. ARANA
  • Publication number: 20150276375
    Abstract: Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line monitoring of both resist footing defects and conductive trace undercut defects. The defects may be detected at the interface between dry film resist (DFR) footings and conductive trace footing formed on insulating layer top surfaces of a packaging substrate. Such footing and undercut defects may other wise be considered “hidden defects”. Using the WLI microscope with a tilted objective lens provides a high-throughput and low cost metrology and tool for non-destructive, non-contact, in-line monitoring.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Shuhong Liu, Zhiyong Wang, Nilanjan Ghosh, Deepak Goyal
  • Publication number: 20150255414
    Abstract: Embodiments of the present disclosure describe solder compounds for electrically coupling integrated circuit (IC) substrates as well as methods for using the solder compounds to couple IC subtrates. The solder compounds are formulated with lower Copper (Cu) percentages to prevent the formation of Cu rich intermettalic compounds (IMCs) which may undergo transitions at elevated temperatures resulting in void formation when NiPdAu or NiAu surface finishes are used on both sides of the solder interconnect. Additionally, nickel (Ni), may be included in the solder compounds to improve fatigue and/or creep properties. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Inventors: Pilin Liu, Yan Li, Deepak Goyal
  • Patent number: 8122401
    Abstract: A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, the transformation identifies a word-level functionality of the at least some of the finite portions by converting bit-level functionality into word-level functionality.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Calypto Design Systems, Inc.
    Inventors: Pankaj P. Chauhan, Deepak Goyal, Anmol Mathur
  • Patent number: 8117571
    Abstract: A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, an abstraction is performed on the netlist.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 14, 2012
    Assignee: Calypto Design Systems, Inc.
    Inventors: Pankaj P. Chauhan, Deepak Goyal, Anmol Mathur
  • Patent number: 7350168
    Abstract: A system, method and computer program product are provided for equivalency checking between a first design and a second design having sequential differences. To accomplish the equivalency checking, sequential differences between a first design and a second design are identified. It is then determined whether the first design and the second design are equivalent, utilizing the identified sequential differences.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: March 25, 2008
    Assignee: Calypto Design Systems, Inc.
    Inventors: Anmol Mathur, Nikhil Sharma, Deepak Goyal, Gagan Hasteer, Rajarshi Mukherjee
  • Patent number: 7287235
    Abstract: A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit by using additional circuitry to obtain a fixed delay circuit. If the fixed delay circuit is a logic circuit that performs multiple cycle computations, it is converted to a logic circuit that performs the same computation in a single cycle. Circuit acceleration includes concatenating multiple copies of the fixed delay circuit. After performing circuit acceleration on all sub-circuits in the fixed delay circuit, a combined accelerated circuit is obtained. Thereafter, redundant flip-flops are identified and removed from the combined accelerated circuit and the combined accelerated circuit is optimized.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: October 23, 2007
    Assignee: Calypto Design Systems, Inc.
    Inventors: Gagan Hasteer, Deepak Goyal
  • Patent number: 7280190
    Abstract: Apparatuses, methods, and systems associated with and/or having components capable of, isolating defects in microelectronic packages are disclosed herein. In various embodiments, a defect-isolation apparatus may include an optoelectronic module to convert an optical test signal to an electrical test signal and provide the electrical test signal to a device under test; an electro-optic probe including an electro-optic crystal to polarize an optical sampling signal upon application of an electrical test signal reflected from the device under test to the electro-optic crystal; and an output module configured to receive the polarized optical sampling signal, and produce an electrical output signal as a function of time based at least in part on the polarized optical sampling signal, the electrical output signal adapted to facilitate isolation of the location(s) of the defect(s) in the device under test.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Zhiyong Wang, Rajendra Dias, Deepak Goyal