Patents by Inventor Deepak Mathew

Deepak Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10638346
    Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Parvathanathan Subrahmanya, Qiang Shen, Aamod Dinkar Khandekar, Mariam Motamed, Wanshi Chen, Hanfang Pan, Deepak Mathew
  • Patent number: 10466967
    Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Deepak Mathew, Ajay Anant Ingle, Yurong Sun, Jianming Zhu, Marc Hoffman
  • Publication number: 20180032311
    Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Deepak Mathew, Ajay Anant Ingle, Yurong Sun, Jianming Zhu, Marc Hoffman
  • Publication number: 20170094545
    Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity.
    Type: Application
    Filed: August 11, 2016
    Publication date: March 30, 2017
    Inventors: Parvathanathan Subrahmanya, Qiang Shen, Aamod Dinkar Khandekar, Mariam Motamed, Wanshi Chen, Hanfang Pan, Deepak Mathew
  • Patent number: 9363749
    Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 7, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Deepak Mathew, Garret Webster Shih, Jose Fridman, Robin Lee Brown
  • Patent number: 9342479
    Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 17, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jose Fridman, Ajay Anant Ingle, Deepak Mathew, Marc M. Hoffman, Michael John Lopez
  • Patent number: 9268571
    Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: February 23, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Marc M. Hoffman, Deepak Mathew
  • Patent number: 9130786
    Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 8, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Deepak Mathew, Ajay Anant Ingle, Mao Zeng, Marc M. Hoffman
  • Publication number: 20150052330
    Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Marc Murray Hoffman, Deepak Mathew, Mao Zeng
  • Publication number: 20140281368
    Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Ajay Anant Ingle, Lucian Codrescu, David J. Hoyle, Jose Fridman, Marc M. Hoffman, Deepak Mathew
  • Publication number: 20140270017
    Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Deepak Mathew, Ajay Anant Ingle, Mao Zeng, Marc M. Hoffman
  • Publication number: 20140115227
    Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Marc M. Hoffman, Deepak Mathew
  • Publication number: 20140071869
    Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).
    Type: Application
    Filed: August 15, 2013
    Publication date: March 13, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Deepak MATHEW, Garret Webster SHIH, Jose FRIDMAN, Robin L. BROWN
  • Publication number: 20140059323
    Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Applicant: Qualcomm Incorporated
    Inventors: Jose Fridman, Ajay Anant Ingle, Deepak Mathew, Marc M. Hoffman, Michael John Lopez
  • Patent number: 8358988
    Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: January 22, 2013
    Assignee: MediaTek Inc.
    Inventors: Lidwine Martinot, Deepak Mathew, Krishnan Vishwanathan, Eric Aardoom, Aiguo Yan, Timothy Fisher-Jeffes
  • Patent number: 8358987
    Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: January 22, 2013
    Assignee: MediaTek Inc.
    Inventors: Deepak Mathew, Aiguo Yan, Krishnan Vishwanathan, Eric Aardoom, Timothy Fisher-Jeffes
  • Patent number: 8316378
    Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: November 20, 2012
    Assignee: MediaTek Inc.
    Inventors: John Zijun Shen, Carsten Aagaard Pedersen, Deepak Mathew, Paul Donald Krivacek, Aiguo Yan, Timothy Perrin Fisher-Jeffes
  • Patent number: 8149702
    Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: April 3, 2012
    Assignee: MediaTek Inc.
    Inventors: Deepak Mathew, Eric Aardoom, Timothy Perrin Fisher-Jeffes, David Stephen Ivory, Carsten Aagaard Pedersen, Aiguo Yan
  • Patent number: 8094641
    Abstract: A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 10, 2012
    Assignee: MediaTek Inc.
    Inventors: Deepak Mathew, Russ Mestechkin, Prahallada Ponnathota, Thomas F. Howe, Timothy Perrin Fisher-Jeffes
  • Patent number: 8054922
    Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: November 8, 2011
    Assignee: MediaTek Inc.
    Inventors: Carsten Aagaard Pedersen, John Zijun Shen, Aiguo Yan, Deepak Mathew, Marko Kocic, Timothy Perrin Fisher-Jeffes, Thomas Keller