Abstract: Improved methods of annealing a workpiece are disclosed. Lasers are used to both increase the temperature of the workpiece, and to laser melt anneal the workpiece. By utilizing lasers for both operations, the manufacturing complexity is reduced. Furthermore, laser melt anneal may provide better junctions and more well defined junction depths. By heating the workpiece either immediately before or after the laser melt anneal, the quality of the junction may be improved. Shallow annealing may be accomplished and annealing may occur in the presence of a species to form a passivation layer. If the workpiece is a solar cell, in-situ heating may improve open circuit voltage (Voc) or dark currents. Insitu heating of the substrate lowers the melting threshold of the substrate and also increases light absorption in the substrate. This reduces the power of the melt laser and hence reduces the residual damage.

Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.

Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.

Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.

Abstract: Dark currents within a photosensitive device are reduced through improved implantation of a species during its fabrication. Dark currents can be caused by defects in the photo-diode device, caused during the annealing, implanting or other processing steps used during fabrication. By amorphizing the workpiece in the photo-diode region, the number of defects can be reduced thereby reducing this cause of dark current. Dark current is also caused by stress induced by an adjacent STI, where the stress caused by the liner and fill material exacerbate defects in the workpiece. By amorphizing the sidewalls and bottom surface of the trench, defects created during the etching process can be reduced. This reduction in defects also decreases dark current in the photosensitive device.

Abstract: A method of implantation that minimizes surface damage to a workpiece is disclosed. In one embodiment, following a doping implant, a second implant is performed which causes the silicon at the surface of the workpiece to become amorphous. This reduces surface damage and interstitials, which has several benefits. First, inactive dopant clusters may become activated due to the replenishment of silicon. Secondly, the amorphous nature of the silicon makes it bond more easily in subsequent process steps, such as silicidation.

Abstract: An improved process of substrate cleaving and a device to perform the cleaving are disclosed. In the traditional cleaving process, a layer of microbubbles is created within a substrate through the implantation of ions of a gaseous species, such as hydrogen or helium. The size and spatial distribution of these microbubbles is enhanced through the use of ultrasound energy. The ultrasound energy causes smaller microbubbles to join together and also reduces the straggle. An ultrasonic transducer is acoustically linked with the substrate to facilitate these effects. In some embodiments, the ultrasonic transducer is in communication with the platen, such that ultrasound energy can be applied during ion implantation and/or immediately thereafter. In other embodiments, the ultrasonic energy is applied to the substrate during a subsequent process, such as an anneal.

Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.

Abstract: A method of detecting interconnect defects in a semiconductor device. The method comprises positioning a portion of a semiconductor substrate, having a plurality of interconnects, in a field of view of an inspection tool. A voltage contrast image of the portion is produced. The voltage contrast image is obtained using a collection field that is at least about 1 percent different than an incident field. The method further comprises using the voltage contrast image to determine defective ones of the interconnects.

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract: Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.

Abstract: The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other steps, placing a substrate 290 in an enclosure 200 being substantially devoid of unwanted contaminants and forming a material layer 310 over the substrate 290 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants. The electroplating process further includes forming a thin layer of oxide 410 over the material layer 310 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants during the forming the thin layer of oxide 410.

Abstract: The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image is obtained using a collection field that is stronger than an incident field. The method further comprises using (130) the voltage contrast image to determine a metal silicide defect in a microelectronic device. Other aspects of the present invention include an inspection system (200) for detecting metal silicide defects and a method of manufacturing an integrated circuit (300).

Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

Abstract: The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). The measurement system measures an electrical value at a plurality of locations along a surface of the wafer, prior to and after exposure of the surface to an activation system (112). The activation system is provided to cause any copper contamination along the surface to form a precipitate thereon. An analysis component (110) is provided to receive electrical value and location information from the measurement system and to identify, from the measurements, the presence and location of copper contamination along the semiconductor wafer surface.