Patents by Inventor Deepak Ramappa
Deepak Ramappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8507298Abstract: At least part of a dielectric layer is implanted to form implanted regions. The implanted regions affect the etch rate of the dielectric layer during the formation of the openings through the dielectric layer. Metal contacts may be formed within these openings. The dielectric layer, which may be SiO2 or other materials, may be part of a solar cell or other device.Type: GrantFiled: December 2, 2011Date of Patent: August 13, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Deepak A. Ramappa
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Patent number: 8466039Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.Type: GrantFiled: February 17, 2012Date of Patent: June 18, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak A. Ramappa, Julian G. Blake
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Patent number: 8465909Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.Type: GrantFiled: November 1, 2010Date of Patent: June 18, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas P. T. Bateman, Helen L. Maynard, Benjamin B. Riordon, Christopher R. Hatem, Deepak Ramappa
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Patent number: 8461030Abstract: A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.Type: GrantFiled: November 16, 2010Date of Patent: June 11, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Anthony Renau, Ludovic Godet, Timothy J. Miller, Joseph C. Olson, Vikram Singh, James Buonodono, Deepak A. Ramappa, Russell J. Low, Atul Gupta, Kevin M. Daniels
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Patent number: 8461032Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.Type: GrantFiled: March 4, 2009Date of Patent: June 11, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas Bateman, Atul Gupta, Christopher Hatem, Deepak Ramappa
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Publication number: 20130143353Abstract: At least part of a dielectric layer is implanted to form implanted regions. The implanted regions affect the etch rate of the dielectric layer during the formation of the openings through the dielectric layer. Metal contacts may be formed within these openings. The dielectric layer, which may be SiO2 or other materials, may be part of a solar cell or other device.Type: ApplicationFiled: December 2, 2011Publication date: June 6, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventor: Deepak Ramappa
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Publication number: 20130064989Abstract: A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.Type: ApplicationFiled: September 10, 2012Publication date: March 14, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Ludovic Godet, Louis Steen, Deepak A. Ramappa
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Publication number: 20130005155Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATE, INC.Inventors: Deepak RAMAPPA, Kyu-Ha SHIM
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Publication number: 20120288637Abstract: Methods of affecting a material's properties through the implantation of ions, such as by using a plasma processing apparatus with a plasma sheath modifier. In this way, properties such as resistance to chemicals, adhesiveness, hydrophobicity, and hydrophilicity, may be affected. These methods can be applied to a variety of technologies. In some cases, ion implantation is used in the manufacture of printer heads to reduce clogging by increasing the materials hydrophobicity. In other embodiments, MEMS and NEMS devices are produced using ion implantation to change the properties of fluid channels and other structures. In addition, ion implantation can be used to affect a material's resistance to chemicals, such as acids.Type: ApplicationFiled: May 14, 2012Publication date: November 15, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, Christopher Hatem, Deepak Ramappa, Xianfeng Lu, Anthony Renau, Patrick Martin
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Publication number: 20120289030Abstract: Methods of creating porous materials, such as silicon, are described. In some embodiments, plasma sheath modification is used to create ion beams of various incidence angles. These ion beams may, in some cases, form a focused ion beam. The wide range of incidence angles allows the material to be deposited amorphously. The porosity and pore size can be varied by changing various process parameters. In other embodiments, porous oxides can be created by adding oxygen to previously created layers of porous material.Type: ApplicationFiled: May 11, 2012Publication date: November 15, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, Xianfeng Lu, Deepak Ramappa
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Patent number: 8283265Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: GrantFiled: December 17, 2009Date of Patent: October 9, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak Ramappa, Kyu-Ha Shim
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Publication number: 20120156860Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.Type: ApplicationFiled: February 17, 2012Publication date: June 21, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Deepak RAMAPPA, Julian G. BLAKE
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Patent number: 8187979Abstract: Methods to texture or fabricate workpieces are disclosed. The workpiece may be, for example, a solar cell. This texturing may involve etching or localized sputtering using a plasma where a shape of a boundary between the plasma and the plasma sheath is modified with an insulating modifier. The workpiece may be rotated in between etching or sputtering steps to form pyramids. Regions of the workpiece also may be etched or sputtered with ions formed from a plasma adjusted by an insulating modifier and doped. A metal layer may be formed on these doped regions.Type: GrantFiled: December 23, 2009Date of Patent: May 29, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak A. Ramappa, Ludovic Godet
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Patent number: 8183546Abstract: Ions are generated and directed toward a workpiece. A laser source generates a laser that is projected above the workpiece in a line. As the laser is generated, a fraction of the ions are blocked by the laser. This may enable selective implantation or modification of the workpiece. In one particular embodiment, the lasers are generated while ions are directed toward the workpiece and then stopped. Ions are still directed toward the workpiece after the lasers are stopped.Type: GrantFiled: February 25, 2010Date of Patent: May 22, 2012Assignee: VARIAN Semiconductor Equipment Associates, Inc.Inventor: Deepak A. Ramappa
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Patent number: 8153496Abstract: An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A patterned implant is performed to introduce a first dopant to a portion of the solar cell. After this implant is done, an oxidation layer is grown on the surface. The oxide layer grows more quickly over the implanted region than over the non-implanted region. An etching process is then performed to remove a thickness of oxide, which is equal to the thickness over the non-implanted regions. A second blanket implant is then performed. Due to the presence of oxide on portions of the solar cell, this blanket implant only implants ions in those regions which were not implanted previously.Type: GrantFiled: March 7, 2011Date of Patent: April 10, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Deepak Ramappa
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Patent number: 8148237Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.Type: GrantFiled: August 5, 2010Date of Patent: April 3, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak Ramappa, Julian G. Blake
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Publication number: 20120074117Abstract: Improved methods of annealing a workpiece are disclosed. Lasers are used to both increase the temperature of the workpiece, and to laser melt anneal the workpiece. By utilizing lasers for both operations, the manufacturing complexity is reduced. Furthermore, laser melt anneal may provide better junctions and more well defined junction depths. By heating the workpiece either immediately before or after the laser melt anneal, the quality of the junction may be improved. Shallow annealing may be accomplished and annealing may occur in the presence of a species to form a passivation layer. If the workpiece is a solar cell, in-situ heating may improve open circuit voltage (Voc) or dark currents. Insitu heating of the substrate lowers the melting threshold of the substrate and also increases light absorption in the substrate. This reduces the power of the melt laser and hence reduces the residual damage.Type: ApplicationFiled: September 21, 2011Publication date: March 29, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Deepak Ramappa, Paul Sullivan
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Publication number: 20120077305Abstract: Methods of enabling the use of high wavelength lasers to create shallow melt junctions are disclosed. In some embodiments, the substrate may be preamorphized to change its absorption characteristics prior to the implantation of a dopant. In other embodiments, a single implant may serve to amorphize the substrate and provide dopant. Once the substrate is sufficiently amorphized, a laser melt anneal may be performed. Due to the changes in the absorption characteristics of the substrate, longer wavelength lasers may be used for the anneal, thereby reducing cost.Type: ApplicationFiled: September 21, 2011Publication date: March 29, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventor: Deepak Ramappa
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Publication number: 20110275173Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.Type: ApplicationFiled: May 2, 2011Publication date: November 10, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Fareen Adeni Khaja, Deepak Ramappa, San Yu, Chi-Chun Chen
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Publication number: 20110259408Abstract: A method of patterning a substrate includes providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate.Type: ApplicationFiled: April 21, 2011Publication date: October 27, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Deepak A. Ramappa, Ludovic Godet