Patents by Inventor Deepak Ramappa

Deepak Ramappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050164496
    Abstract: The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other steps, placing a substrate 290 in an enclosure 200 being substantially devoid of unwanted contaminants and forming a material layer 310 over the substrate 290 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants. The electroplating process further includes forming a thin layer of oxide 410 over the material layer 310 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants during the forming the thin layer of oxide 410.
    Type: Application
    Filed: January 28, 2004
    Publication date: July 28, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Richard Guldi, Deepak Ramappa
  • Publication number: 20050042886
    Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.
    Type: Application
    Filed: August 21, 2003
    Publication date: February 24, 2005
    Inventors: Aaron Frank, David Gonzalez, John DeGenova, Srinivas Raghavan, Deepak Ramappa
  • Publication number: 20050037525
    Abstract: The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a layer of gate oxide on the semiconductor wafer; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam is directed at the semiconductor wafer; an electron beam inspection tool used to detect passive voltage contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the energy levels vary from about 600 eV to 5000 eV.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventor: Deepak Ramappa