Patents by Inventor Deepak S
Deepak S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250144726Abstract: A modular rotor blade assembly includes a pair of cover plates; a base plate disposed between the pair of cover plates; a wedge disposed within a slot formed in a perimeter of the base plate; and a rotor blade attached to the wedge. One or more cover plates and/or the rotor blade with corresponding wedge are capable of being replaced without the need to replace the base plate, thereby reducing the cost or replacing the entire rotor blade assembly.Type: ApplicationFiled: November 7, 2024Publication date: May 8, 2025Inventors: Vishwanath Lande, Prashanth Suresh, Steef Pronk, Michael Zunner, Akshay A., Deepak S. Achar, Balachandra Hegde
-
Patent number: 12293463Abstract: A method of decomposing a three-dimensional representation of an object into a plurality of convex hulls can include instantiating a cluster priority queue in a computing system memory that initially contains a cluster corresponding to the three-dimensional representation of the object, computing with a processor of the computing system a concavity measure for each cluster in the cluster priority queue, and, for the cluster with the highest concavity measure: (1) computing with the processor a cut plane that divides the cluster corresponding to the three-dimensional representation of the object into two new clusters, each of the two new clusters having a corresponding convex hull, wherein computing a cut plane includes performing a hierarchical search of potential cut planes, (2) removing the cluster corresponding to the three-dimensional representation of the object from the cluster priority queue, and (3) adding the two new clusters to the cluster priority queue.Type: GrantFiled: April 28, 2022Date of Patent: May 6, 2025Assignee: Apple Inc.Inventors: Khaled Mammou, Adrian A Biagioli, Deepak S Tolani
-
Publication number: 20250137328Abstract: A drill-bit may include a head which includes a face and a gage. The face may include a plurality of face button bits. The gage may include a plurality of gage button bits evenly spaced around the head. A plurality of major chip gage gashes may be evenly spaced around the head. A plurality of minor chip gage gashes may be evenly spaced around the head. An axis extending through centers of the plurality of face button bits may extend through one of the plurality of major chip gage gashes and one of the plurality of minor chip gage gashes. The plurality of major chip gage gashes may alternate with the plurality of minor chip gage gashes around the head. One of the plurality of gage button bits may be disposed in-between every set of the alternating major chip gage gashes and minor chip gage gashes.Type: ApplicationFiled: October 29, 2024Publication date: May 1, 2025Inventors: Nagesh Kumar GK, Mahesh Magadaiah, Deepak S. Achar, Prashanth Suresh, Srihari Varma, Balachandra Hegde
-
Patent number: 12288287Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.Type: GrantFiled: February 8, 2024Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
-
Publication number: 20250047517Abstract: A switch receives a first query which requests a response from all hosts in the network, wherein the switch is a next-hop switch of a first set of the hosts in a multicast group, wherein the first query is an Internet Group Management Protocol (IGMP) all-host query message, and wherein the first query is generated by an IGMP querying host and transmitted via one or more intermediate switches. The switch tracks join messages received from the first set of the hosts in response to the first query, wherein a respective join message indicates that a corresponding host is to remain in the multicast group. Responsive to determining that the tracked join messages meet a predetermined threshold, the switch consolidates the tracked join messages by forwarding a reduced number of join messages, thereby reducing a total number of join messages propagated to the IGMP querying host via the intermediate switches.Type: ApplicationFiled: July 31, 2023Publication date: February 6, 2025Inventors: Deepak S. Kudachi, Tathagata Nandy, Chethan Chavadibagilu Radhakrishnabhat
-
Patent number: 12199858Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for traffic control for application-independent service mesh. In one example, processor circuitry to perform operations to instantiate ingress traffic management circuitry to receive ingress traffic events, at least one of the ingress traffic events to request access to a target microservice running on the second endpoint. The processor circuitry further performs operations to instantiate virtual service authorization circuitry to perform a look up of an authorization policy to the target microservice in the microservice catalog. Finally, the processor circuitry performs operations to instantiate endpoint selection circuitry to select the second endpoint to service the ingress traffic event in response to the authorization policy allowing access to the target microservice.Type: GrantFiled: April 1, 2022Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Deepak S, Kannan Babu Ramia, Palaniappan Ramanathan
-
Patent number: 12141015Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.Type: GrantFiled: December 18, 2020Date of Patent: November 12, 2024Assignee: Intel CorporationInventors: Deepak S Kirubakaran, Ramakrishnan Sivakumar, Russell Fenger, Monica Gupta, Jianwei Dai, Premanand Sakarda, Guy Therien, Rajshree Chabukswar, Chad Gutierrez, Renji Thomas
-
Publication number: 20240355032Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.Type: ApplicationFiled: February 8, 2024Publication date: October 24, 2024Inventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
-
Patent number: 12126592Abstract: Systems and methods may be used to provide neutral host edge services in an edge network. An example method may include generating a virtual machine for a communication service provider at a compute device. The method may include receiving a user packet originated at a user device associated with the communication service provider and identifying dynamic route information related to the user packet using the virtual machine corresponding to the communication service provider. Data may be output corresponding to the user packet based on the dynamic route information.Type: GrantFiled: December 26, 2020Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Kannan Babu Ramia, Deepak S, Palaniappan Ramanathan, Timothy Verrall, Francesc Guim Bernat
-
Publication number: 20240346979Abstract: In one example, a head mounted display system includes at least one memory; and at least one processor to execute instructions to: detect a first position and a first view direction of a head of a user based on sensor data generated by at least one of an accelerometer, at least one camera, or a gyroscope at a first point in time; determine a latency associated with a time to cause an image to be presented on the display; determine a predicted position and a predicted view direction of the head of the user at a second point in time based on the latency; render, prior to the second point in time, the image for presentation on the display based on the predicted position and the predicted view direction of the head of the user; and cause the display to present the rendered image.Type: ApplicationFiled: June 6, 2024Publication date: October 17, 2024Inventors: Atsuo Kuwahara, Deepak S. Vembar, Paul S. Diefenbaugh, Vallabhajosyula S. Somayazulu, Kofi C. Whitney
-
Patent number: 12046183Abstract: In one example, a head mounted display system includes at least one memory; and at least one processor to execute instructions to: detect a first position and a first view direction of a head of a user based on sensor data generated by at least one of an accelerometer, at least one camera, or a gyroscope at a first point in time; determine a latency associated with a time to cause an image to be presented on the display; determine a predicted position and a predicted view direction of the head of the user at a second point in time based on the latency; render, prior to the second point in time, the image for presentation on the display based on the predicted position and the predicted view direction of the head of the user; and cause the display to present the rendered image.Type: GrantFiled: June 13, 2023Date of Patent: July 23, 2024Assignee: INTEL CORPORATIONInventors: Atsuo Kuwahara, Deepak S. Vembar, Paul S. Diefenbaugh, Vallabhajosyula S. Somayazulu, Kofi C. Whitney
-
Patent number: 11954783Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2021Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
-
Publication number: 20240106900Abstract: Methods, apparatus, systems, and articles of manufacture to add a non-native node to a cluster are disclosed. An example apparatus includes programmable circuitry to at least one of instantiate a first agent to interface with a management application to obtain a request from a node to join a cluster of nodes, the first agent to interface with the management application using a first protocol; and instantiate a second agent which employs a second protocol different than the first protocol: responsive to an authentication of an identity credential of the node, obtain a secret credential; and cause the first agent to pass the secret credential to the node via the management application to enable the node to join the cluster of nodes.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Inventors: Kannan Babu Ramia, Palaniappan Ramanathan, Deepak S, Bhavik Dhandhalya
-
Publication number: 20240078738Abstract: A system compresses and decompresses attribute information for visual volumetric content, such as a mesh representation. Attribute values are included in the visual volumetric representation, wherein at least some of the attribute values include unitary vectors, such as surface normal vectors or surface tangent vectors having a magnitude of one unit. In order to compress the attribute information the three-dimensional unit vectors are mapped into two dimensional parametric coordinates for a planar representation of a unit sphere. To reduce negative effects on compression due to distortion or discontinuities in the planar representation, mappings for compressing respective unit vectors are adaptively selected.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Applicant: Apple Inc.Inventors: Khaled Mammou, Deepak S. Tolani, Alexandros Tourapis
-
Patent number: 11887360Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data captured by one or more sensors associated with a first device. Further, the processor comprises circuitry to: access the sensor data captured by the one or more sensors associated with the first device; determine that an incident occurred within a vicinity of the first device; identify a first collection of sensor data associated with the incident, wherein the first collection of sensor data is identified from the sensor data captured by the one or more sensors; preserve, on the memory, the first collection of sensor data associated with the incident; and notify one or more second devices of the incident, wherein the one or more second devices are located within the vicinity of the first device.Type: GrantFiled: October 8, 2021Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Shao-Wen Yang, Eve M. Schooler, Maruti Gupta Hyde, Hassnaa Moustafa, Katalin Klara Bartfai-Walcott, Yen-Kuang Chen, Jessica McCarthy, Christina R. Strong, Arun Raghunath, Deepak S. Vembar
-
Patent number: 11854112Abstract: A system compresses and decompresses attribute information for visual volumetric content, such as a mesh representation. Attribute values are included in the visual volumetric representation, wherein at least some of the attribute values include unitary vectors, such as surface normal vectors or surface tangent vectors having a magnitude of one unit. In order to compress the attribute information the three-dimensional unit vectors are mapped into two dimensional parametric coordinates for a planar representation of a unit sphere. To reduce negative effects on compression due to distortion or discontinuities in the planar representation, mappings for compressing respective unit vectors are adaptively selected.Type: GrantFiled: May 17, 2022Date of Patent: December 26, 2023Assignee: Apple Inc.Inventors: Khaled Mammou, Deepak S Tolani, Alexandros Tourapis
-
Publication number: 20230410720Abstract: In one example, a head mounted display system includes at least one memory; and at least one processor to execute instructions to: detect a first position and a first view direction of a head of a user based on sensor data generated by at least one of an accelerometer, at least one camera, or a gyroscope at a first point in time; determine a latency associated with a time to cause an image to be presented on the display; determine a predicted position and a predicted view direction of the head of the user at a second point in time based on the latency; render, prior to the second point in time, the image for presentation on the display based on the predicted position and the predicted view direction of the head of the user; and cause the display to present the rendered image.Type: ApplicationFiled: June 13, 2023Publication date: December 21, 2023Inventors: Atsuo Kuwahara, Deepak S. Vembar, Paul S. Diefenbaugh, Vallabhajosyula S. Somayazulu, Kofi C. Whitney
-
Patent number: 11829525Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.Type: GrantFiled: April 19, 2021Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, James M. Holland, Pattabhiraman K, Sayan Lahiri, Radhakrishnan Venkataraman, Kamal Sinha, Ankur N. Shah, Deepak S. Vembar, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall
-
Publication number: 20230351697Abstract: A method of decomposing a three-dimensional representation of an object into a plurality of convex hulls can include instantiating a cluster priority queue in a computing system memory that initially contains a cluster corresponding to the three-dimensional representation of the object, computing with a processor of the computing system a concavity measure for each cluster in the cluster priority queue, and, for the cluster with the highest concavity measure: (1) computing with the processor a cut plane that divides the cluster corresponding to the three-dimensional representation of the object into two new clusters, each of the two new clusters having a corresponding convex hull, wherein computing a cut plane includes performing a hierarchical search of potential cut planes, (2) removing the cluster corresponding to the three-dimensional representation of the object from the cluster priority queue, and (3) adding the two new clusters to the cluster priority queue.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Khaled Mammou, Adrian A Biagioli, Deepak S Tolani
-
Patent number: 11795370Abstract: Compositions and methods of using such compositions to inhibit the formation of gas hydrate agglomerates are provided. In certain embodiments, the methods include: contacting a fluid with a hydrate inhibitor composition that includes at least one compound having the structural formula (I) wherein R1 is hydrogen or any C1 to C8 hydrocarbon chain; each of R2 and R3 is independently a C1 to C8 hydrocarbon chain; R4 is hydrogen, a C1 to C20 hydrocarbon chain, or —CH2—CH(OH)—R5; R5 is a C1 to C50 alkyl chain or a C1 to C50 alkenyl chain; X? is a counter anion; and n is an integer from 1 to 8.Type: GrantFiled: September 25, 2018Date of Patent: October 24, 2023Assignee: Halliburton Energy Services, Inc.Inventors: Qiang Lan, Deepak S. Monteiro