Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the first single crystal transistors or second transistors include at least two FinFet transistors each having different threshold voltages.

Abstract: A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

Abstract: Thermal Management Systems for electronic devices and related methods are disclosed. An example electronic housing includes a housing defining a cavity, electronics in the cavity, and a touch display over the electronics. A heat spreader has a first surface toward the electronics and a second surface opposite the first surface toward the touch display, where the heat spreader is to dissipate heat generated by the electronics. A glass cover is coupled to the housing and has a first side toward the touch display and a second side opposite the first side, where the glass cover is exposed external to the housing. An insulation layer is between the second surface of the heat spreader and the second side of the glass cover to restrict heat transfer from the electronics to the second side of the glass cover.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the first single crystal transistors or second transistors include at least two FinFet transistors each having different threshold voltages.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the second level includes second ESD circuits.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the second level includes second ESD circuits.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, one or more heat sources over the substrate, one or more heat pipes thermally coupled to the one or more heat sources, a heat spreader coupled to the one or more heat pipes, where the heat spreader is in-plane with the heat pipe, and one or more loading mechanisms coupled to at least a portion of the one or more heat pipes and to the substrate. The one or more loading mechanisms are in-plane with the spreader and the one or more heat pipes.

Abstract: Techniques are described to address issues for repairing and/or servicing electronic components through the use of retaining assemblies that use bimetal retaining mechanisms. The bimetal retaining mechanisms may comprise various shapes such as hooks, snap-hooks, clips, etc., and facilitate a temperature-selective removal of various electronic components such as displays, EMI shields, etc. without damaging these components and without compromising the thickness and weight of the electronic device. External heating systems may be used to trigger actuation of the bimetal retaining mechanisms, resulting in their release. Alternatively, internal electronic device heating systems may be used.

Abstract: A system, method, and computer program product are disclosed. The method includes receiving a first text unit, extracting features from the first text unit, receiving a second text unit, extracting features from the second text unit, receiving a portion comprising the first text unit and the second text unit, and aggregating the features extracted from the first text unit and the features extracted from the second text unit. The method also includes generating a set of scores for the first text unit, the second text unit, and the portion, and based on the set of scores, selecting at least one ground truth candidate from the first text unit, the second text unit, and the portion. Additionally, the method includes determining that the at least one ground truth candidate includes at least one confirmed ground truth, and adding the at least one confirmed ground truth to a ground truth repository.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid including at least one second transistor, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid including at least one second transistor, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

Abstract: Low-profile fasteners with springs that are either integrated with the fastener or are a physically separate component can provide a more evenly distributed load to a heat transfer device, such as a vapor chamber or a heat pipe. The low-profile fasteners do not increase the height of the base of a mobile computing device as the spring and the portion of the fastener that extends past the spring fit within a recess or cavity of the heat transfer device. The spring can be a diaphragm spring, a wave spring, or another suitable spring. The use of low-profile fasteners with springs to fasten a heat transfer device to a mainboard may allow for designs with a smaller mainboard area, which can leave room for a larger thermal management solution (which can increase cooling capacity) and allow for a greater thermal design power for the system.

Abstract: A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

Abstract: A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

Abstract: A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming a plurality of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing a first etch step; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth metal layer above; forming a connection to the second metal layer which includes a via through the second level; forming a fifth metal layer above, where some second transistors include a metal gate, and the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.