Patents by Inventor Deepak Sekar

Deepak Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210112684
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, one or more heat sources over the substrate, one or more heat pipes thermally coupled to the one or more heat sources, a heat spreader coupled to the one or more heat pipes, where the heat spreader is in-plane with the heat pipe, and one or more loading mechanisms coupled to at least a portion of the one or more heat pipes and to the substrate. The one or more loading mechanisms are in-plane with the spreader and the one or more heat pipes.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventors: Penchala Pratap Binni Boyina, Kathiravan D, Babu Triplicane Gopikrishnan, Prakash Kurma Raju, Deepak Sekar, Hari Shanker Thakur
  • Patent number: 10903089
    Abstract: A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said second level comprises at least one Phase Lock Loop (“PLL) circ
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 26, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Publication number: 20210020457
    Abstract: A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said second level comprises at least one Phase Lock Loop (“PLL) circ
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10892169
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 12, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10677038
    Abstract: A method includes automatically creating one or more test schedules for a well test of one or more wells in an oil or gas production environment. The method also includes automatically creating one or more test frames for use in generation of the well test. The method further includes, following execution of the test frame, automatically validating one or more test records generated during the one or more test frames. In addition, the method includes automatically creating the well test for determining one or more well characteristics.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 9, 2020
    Assignee: Honeywell International Inc.
    Inventors: Girish Venkatasubbarao, Michele Loseto, Ramanuja Puasapati, Nitin Garg, Nivas Sekar, Deepak Dhanapal
  • Patent number: 10651054
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 12, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10600657
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 24, 2020
    Assignee: MONOLITHIC 3D INC
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10366970
    Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 30, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Publication number: 20190188623
    Abstract: In an approach for providing a cognitive and dynamic business process, based on a user's natural language input, a processor receives information from a user, wherein the information includes natural language input. A processor analyzes the information from the user, using natural language processing. A processor generates a cognitive and dynamic business process, wherein the cognitive and dynamic business process assists the user to determine a solution to a problem. A processor delivers the cognitive and dynamic business process, wherein the delivered cognitive and dynamic business process includes a request for feedback. A processor analyzes the feedback, wherein the cognitive and dynamic business process is tagged with the feedback and stored, and wherein the feedback is based on feedback from the user and a subject matter expert.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Deepak Sekar, Salil Ahuja, Debojyoti Mookerjee, William J. Shondelmyer
  • Publication number: 20190019693
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 17, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Publication number: 20190013213
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
    Type: Application
    Filed: August 27, 2018
    Publication date: January 10, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Publication number: 20190006192
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 3, 2019
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Publication number: 20180331073
    Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).
    Type: Application
    Filed: July 2, 2018
    Publication date: November 15, 2018
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 10115663
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 30, 2018
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10043781
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.
    Type: Grant
    Filed: February 25, 2018
    Date of Patent: August 7, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 10037691
    Abstract: An approach is provided in which an information handling system detects a traffic infraction of a driver driving a vehicle. In turn, the information handling system forms an infraction detection zone that includes a set of traffic control devices, and sends a set of configuration parameters to the set of traffic control devices. The information handling system then uses vehicle identification data in the set of configuration parameters to identify driving behaviors of the driver through the infraction detection zone and issues a citation based upon the identified driving behaviors.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Deepak Sekar, William J. Shondelmyer
  • Publication number: 20180197812
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Publication number: 20180190619
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.
    Type: Application
    Filed: February 25, 2018
    Publication date: July 5, 2018
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 9953972
    Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 24, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 9941275
    Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 10, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar