Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

Abstract: An approach is provided in which an information handling system detects a traffic infraction of a driver driving a vehicle. In turn, the information handling system forms an infraction detection zone that includes a set of traffic control devices, and sends a set of configuration parameters to the set of traffic control devices. The information handling system then uses vehicle identification data in the set of configuration parameters to identify driving behaviors of the driver through the infraction detection zone and issues a citation based upon the identified driving behaviors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.

Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

Abstract: A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power distribution grid to provide power to the first transistors, processing a second layer overlying the first transistors and including second transistors, where the second layer includes a through layer via with diameter of less than 150 nm, forming a second power distribution grid overlaying the second transistors, where the first power distribution grid includes first power conductors and the second power distribution grid includes second power conductors, and where the second power conductors are substantially wider or thicker than the first power conductors, and where the device includes a plurality of vias to connect the second power distribution grid to the first power distribution grid.

Abstract: In an approach for delivering customized messages, a computer receives a request to initiate a communication, wherein the request includes a caller and at least one recipient. The computer determines an identifier associated with the caller and an identifier associated with the at least one recipient from the received request. The computer identifies the caller and the at least one recipient based on the corresponding determined identifiers. The computer retrieves data associated with the identified caller and the identified at least one recipient, wherein the data includes personal information, Internet browsing trends, and listening preferences. The computer determines customized messages for the identified caller and the identified at least one recipient based on the retrieved data associated with the identified caller and the at least one recipient. The computer delivers the determined customized messages to one or more of the identified caller and the identified at least one recipient.

Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.

Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

Abstract: In an approach for delivering customized messages, a computer receives a request to initiate a communication, wherein the request includes a caller and at least one recipient. The computer determines an identifier associated with the caller and an identifier associated with the at least one recipient from the received request. The computer identifies the caller and the at least one recipient based on the corresponding determined identifiers. The computer retrieves data associated with the identified caller and the identified at least one recipient, wherein the data includes personal information, Internet browsing trends, and listening preferences. The computer determines customized messages for the identified caller and the identified at least one recipient based on the retrieved data associated with the identified caller and the at least one recipient. The computer delivers the determined customized messages to one or more of the identified caller and the identified at least one recipient.

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a first circuit including at least one of the first transistors, and the first circuit has a first circuit output connected to at least one of the second transistors, wherein the at least one of the second transistors is connected to a device output that is designed to be connected to external devices, and wherein the at least one of the second transistors is substantially larger than the at least one of the first transistors.

Abstract: An integrated device, including: a first mono-crystal layer including a plurality of image sensor pixels and alignment marks; an overlaying oxide on top of the first mono-crystal layer; and a second mono-crystal layer overlaying the oxide, where the second mono-crystal layer includes a plurality of single crystal transistors aligned to the alignment marks.