Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: Embodiments relate to coordinating the operations of subsystems in a communication system of an electronic device where a coexistence hub device monitors the state information transmitted as coexistence messages over one or more multi-drop buses, processes the monitored coexistence messages and sends out control messages as coexistence messages to other systems on chips (SOCs). The coexistence hub device can also update the operations of the communication system. The coexistence hub device may receive an operation policy from a central processor and may execute the operation policy without further coordination of the central processor. The coexistence hub device broadcasts the control messages as coexistence messages according to the executed operation policy.

Abstract: Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

Abstract: Embodiments relate to a billboard circuit that stores context information received from various component circuits in an electronic device. The context information indicates an operating status of the corresponding component circuit, system or shared resources. The stored context information may be retrieved by one or more component circuits when events (e.g., turning on of a component circuit) are detected. By using the billboard circuit, a component circuit may detect changes in the operating status of other components circuits and configure or update its operations even when the changes occurred while the component circuit was asleep or disabled. The billboard circuit may monitor updating of the context information by the component circuit and initiate notification to other components circuits when certain entries of the context information is updated.

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: Systems, methods, and apparatus for improving throughput of a serial bus are described. A method performed at a device coupled to a serial bus includes detecting a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire of the serial bus, determining that no transition in signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire, defining bit values for the first pair of consecutive bits based on direction of the transition in signaling state detected while the first pair of consecutive bits is being received, and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits.

Abstract: Embodiments relate to coordinating the operations of subsystems in a communication system of an electronic device where a coexistence hub device monitors the state information transmitted as coexistence messages over one or more multi-drop buses, processes the monitored coexistence messages and sends out control messages as coexistence messages to other systems on chips (SOCs). The coexistence hub device can also update the operations of the communication system. The coexistence hub device may receive an operation policy from a central processor and may execute the operation policy without further coordination of the central processor. The coexistence hub device broadcasts the control messages as coexistence messages according to the executed operation policy.

Abstract: Systems, methods, and apparatus for transmitting additional information over a synchronous serial bus are described. A method performed at a transmitting device coupled to the serial bus includes providing first data in a data signal to be transmitted on a first wire of a multi-wire serial bus, providing a series of pulses in a clock signal to be transmitted on a second wire of a multi-wire serial bus, where each pulse has a rising edge and a falling edge, each edge being aligned with a different bit of the first data. The method may include encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data, and transmitting the data signal and the clock signal over the serial bus.

Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: An aspect of the present disclosure includes methods, systems, and computer-readable media for triggering the single signal during the first buffer period to concurrently adjust a first plurality of gain states of a first plurality of low-noise amplifiers associated with a first expected reception of the first symbol on the first component carrier and a second plurality of gain states of a second plurality of low-noise amplifiers associated with a second expected reception of the second symbol on the second component carrier, and receiving the first symbol via the first component carrier and the second symbol via the second component carrier after the first buffer period.

Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

Abstract: Systems, methods, and apparatus for improving latency of a serial bus are described. A method performed at a device coupled to a serial bus includes writing a first data byte received in a first field of a datagram from a serial bus to a first register in the slave device, modifying the address pointer by adding or subtracting a stride value provided in a second field of the datagram to obtain a modified address pointer, and writing a second data byte received in a third field of the datagram to a second register in the slave device. The first register may be located at an address indicated by an address pointer and the second register may be located at an address indicated by the modified address pointer. The first register and the second register may be located at non-contiguous addresses.

Abstract: Systems, methods, and apparatus for improving throughput of a serial bus are described. A method performed at a device coupled to a serial bus includes detecting a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire of the serial bus, determining that no transition in signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire, defining bit values for the first pair of consecutive bits based on direction of the transition in signaling state detected while the first pair of consecutive bits is being received, and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits.

Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

Abstract: A device for activating trigger data has a serial bus interface and a processing circuit coupled to the serial bus interface. The processing circuit is configured to receive a plurality of trigger data via a serial bus, receive a plurality of activation data via the serial bus, detect an activation scheme for activating a respective trigger data of the plurality of trigger data based on activation data corresponding to the respective trigger data, and activate the respective trigger data according to the detected activation scheme. If activated, each one of the plurality of trigger data respectively enables a corresponding operation to be performed at the device. Each one of the plurality of activation data respectively correspond to each one of the plurality of trigger data.

Abstract: Systems, methods, and apparatus for sharing a serial bus interface among devices having different operating speeds are described. A sequence of commands on a data line of the serial bus are generated including a start condition signal and a device identifier signal where the identifier signal is part of a command frame in the sequence of commands. The sequence of commands is transmitted on the data line concurrent with the transmission of a clock signal on a clock line of the serial bus during the duration of the device identifier signal. The frequency of the clock signal is set at a first clock frequency for the duration of the device identifier signal where the first clock frequency is a frequency supported among all devices coupled to the serial bus, allowing all devices to decode an initial sequence, whether the devices are configured for higher frequency operation or not.

Abstract: An aspect of the present disclosure includes methods, systems, and computer-readable media for triggering the single signal during the first buffer period to concurrently adjust a first plurality of gain states of a first plurality of low-noise amplifiers associated with a first expected reception of the first symbol on the first component carrier and a second plurality of gain states of a second plurality of low-noise amplifiers associated with a second expected reception of the second symbol on the second component carrier, and receiving the first symbol via the first component carrier and the second symbol via the second component carrier after the first buffer period.