Abstract: System and methods that cancel artifacts of stimulation signals from neural signals are disclosed. In several embodiments, the systems and methods determine a threshold value for the neural signal in the absence of artifacts. The threshold value can then be used to detect an artifact in received neural signals. In a number of embodiments, a template can be used to cancel an artifact from a neural signal in response to the neural signal being greater than the threshold value.

Abstract: Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine.

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Abstract: Thermoelectric energy harvesting systems in accordance with embodiments of the invention enable energy harvesting. One embodiment includes a thermoelectric energy harvesting (TEH) system comprising a TEH comprising a thin-film array-based TEH source; start-up mode circuitry comprising: an upper branch comprising: a mode switch configured to allow selection of the upper branch; an inductive-load ring oscillator (ILRO); a charge pump configured to receive an input from the ILRO and output current, where output current is utilized to charge an upper branch capacitor; a lower branch comprising: an inductor; an active diode configured to transfer energy stored in the inductor to an output capacitor; maximum-power-point tracking (MPPT) mode circuitry, where the MPPT loop comprises: a mode control unit; a gate controller; a clock generator configured to generate at least one control signal; an analog-domain MPPT unit configured to receive the at least one generated control signal.

Abstract: Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.

Abstract: A high dynamic range sensing front-end for bio-signal recording systems in accordance with embodiments of the invention are disclosed. In one embodiment, a bio-signal amplifier includes an input signal, where the input signal is modulated to a predetermined chopping frequency, a first amplifier stage, a parallel-RC circuit connected to the first amplifier stage and configured to generate a parallel-RC circuit output by selectively blocking an offset current, a second amplifier stage connected to the parallel-RC circuit that includes a second input configured to receive the parallel-RC circuit output and generate a second output that is an amplified version of the input signal with ripple-rejection. Further, the bio-signal amplifier can also include an auxiliary path configured for boosting input impedance by pre-charging at least one input capacitor. In addition, the bio-signal amplifier can also include a DC-servo feedback loop that includes an integrator that utilizes a duty-cycled resistor.

Abstract: Systems and methods for restoring cognitive function are disclosed. In some implementations, a method includes, at a computing device, separately stimulating one or more of lateral and medial entorhinal afferents and other structures connecting to a hippocampus of an animal subject in accordance with a plurality of predefined stimulation patterns, thereby attempting to restore object-specific memories and location-specific memories; collecting a plurality of one or more of macro- and micro-recordings of the stimulation of hippocampalentorhinal cortical (HEC) system; and refining the computational model for restoring individual memories in accordance with a portion of the plurality of one or more of macro- and micro-recordings.

Abstract: Signal recording sensor systems in accordance with embodiments of the invention include sensors capable of sensing and capturing electrophysiological signals in the presence of interference signals, an analog front-end including circuitry configured to record electro-physiological input signals as a voltage, and an analog to digital converter including a voltage-controlled-oscillator configured to convert the recorded analog electrophysiological input signal to a phase output. While such signal recording sensor systems can be used in the recording of biosignals and/or electrophysiological signals generated from living organisms, signal recording sensor systems in accordance with embodiments of the invention are not limited to recording biosignals and/or electrophysiological signals.

Abstract: Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Abstract: Voltage controlled magnetoelectric tunnel junction (MEJ) based content addressable memory is described which provides efficient high speed switching of MEJs toward eliminating any read disturbance of written data. Each cell of said CAM having two MEJs and transistor circuitry for performing a write at voltages of a first polarity, and reads at voltages of a second polarity. If the data searched does not equal the data written in the CAM, then the match line state is changed.

Abstract: Voltage controlled magneto-electric tunnel junctions (MEJ) and associated memory devices are described which provide efficient high speed switching of non-volatile magnetic random access memory (MeRAM) devices at high cell densities with multiple word access mechanisms, including a burst mode write of multiple words, and a back-to-back read of two words in consecutive clock cycles. In at least one preferred embodiment, these accesses are performed in a manner that prevents any possibility of a read disturbance arising.

Abstract: Methods and systems for location-based asset sharing are provided. In an embodiment, a method stores a publication in a data store accessible by a server system, the publication including a publication location and a distance restriction. The method receives a request for the asset and then determines, by the server system, to provide the asset in response to the request. The determining is based on a requesting location associated with the request, the publication location, and the distance restriction, wherein according to the distance restriction, the asset is only provided to the requesting location if a distance from the requesting location to the publication location satisfies a specified relationship. The method provides the asset in response to the request. In another embodiment, the publication includes references to one or more assets being shared by a publisher. Another method creates an asset-listener association in response to a received asset association request.

Abstract: Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine.

Abstract: As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.

Abstract: As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1V supply voltage, which is greater than reference designs achieve at 5 ns performance.

Abstract: Voltage controlled magneto-electric tunnel junctions (MEJ) and associated memory devices are described which provide efficient high speed switching of non-volatile magnetic random access memory (MeRAM) devices at high cell densities with multiple word access mechanisms, including a burst mode write of multiple words, and a back-to-back read of two words in consecutive clock cycles. In at least one preferred embodiment, these accesses are performed in a manner that prevents any possibility of a read disturbance arising.

Abstract: Voltage controlled magnetoelectric tunnel junction (MEJ) based content addressable memory is described which provides efficient high speed switching of MEJs toward eliminating any read disturbance of written data. Each cell of said CAM having two MEJs and transistor circuitry for performing a write at voltages of a first polarity, and reads at voltages of a second polarity. If the data searched does not equal the data written in the CAM, then the match line state is changed.

Abstract: Systems and methods provide a mechanism to print documents having transparent artwork that overlaps other artwork. One aspect of the systems and methods includes sending the document to a printer control system coupled to a printer. The printer control system detects overlapping areas, and processes the artwork into separate atomic regions. Objects contributing to the atomic region are placed in an object stack. A rasterizer having knowledge of the printer characteristics creates object raster buffers for the portions of the objects that contribute to the atomic region. The object raster buffers are then blended according to transparency values associated with the object to create an atomic region raster buffer. The atomic region raster buffer is combined with other atomic region raster buffers and raster images for other non-overlapping objects into a printer raster buffer that may be processed by the printer to produce a page.

Abstract: Methods, systems, and apparatus, including computer program products, for determining a complexity value for a subregion of an electronic document page that includes one or more objects. In one aspect, a method includes dividing a subregion of an electronic document page into a plurality of cells, where the electronic document page includes one or more objects, the objects include one or more transparent objects, the subregion includes at least part of a transparent object, and each cell has an associated cell counter. The method includes, for each object partly or completely located in the subregion, identifying cells that are overlapped by the object, and increasing the associated cell counter for each of the identified cells. The method includes summing all cell counters associated with all cells in the subregion to determine a complexity value for the subregion.