Abstract: Methods, systems, and apparatus, including computer program products, for determining a complexity for a subregion of an electronic document page that includes one or more objects. In one aspect, a method includes dividing a subregion of an electronic document page into a plurality of cells, where the electronic document page includes one or more objects, the objects include one or more transparent objects, the subregion includes at least part of a transparent object, and each cell has an associated cell complexity. The method includes, for each object partly or completely located in the subregion, identifying cells that are overlapped by the object, and increasing the associated cell complexity for each of the identified cells. The method includes combining all cell complexities associated with all cells in the subregion to determine a complexity for the subregion.

Abstract: Edges are detected in a raster image and generate parametric curves from the detected edges. The parametric curves are used to render a scaled version of the raster image. Some embodiments may allow edge locations within a raster image to retain a satisfactory level of sharpness when the raster image is scaled to a larger size.

Abstract: The invention features a method, system, and computer program product. A source bitmap image, a destination bitmap image, a source image feature outline surrounding a source region of the source bitmap image, and a destination image feature outline surrounding a destination region of the destination bitmap image are received. A point-to-point correspondence between the source image feature outline and the destination image feature outline is generated, such that the point-to-point correspondence defines a reshaping of the source image feature outline. An interpolation surface is calculated interpolating an area of the source bitmap image that includes the source region. The interpolation surface is reshaped using the point-to-point correspondence.

Abstract: Computer-implemented methods and apparatus for processing a graphical element that has an associated original type, including blending at least part of the graphical element and at least part of one or more other graphical elements to produce a transformed graphical element. The transformed graphical element has an associated transformed type, and the transformed type is different than the original type. Information about the original type is stored, and the transformed graphical element, an adjacent graphical element, or both are processed using the stored information about the original type.

Abstract: Methods, systems, and apparatus, including computer program products, for determining a complexity value for a subregion of an electronic document page that includes one or more objects. In one aspect, a method includes dividing a subregion of an electronic document page into a plurality of cells, where the electronic document page includes one or more objects, the objects include one or more transparent objects, the subregion includes at least part of a transparent object, and each cell has an associated cell counter. The method includes, for each object partly or completely located in the subregion, identifying cells that are overlapped by the object, and increasing the associated cell counter for each of the identified cells. The method includes summing all cell counters associated with all cells in the subregion to determine a complexity value for the subregion.

Abstract: Computer-implemented methods and apparatus for processing a graphical element that has an associated original type, including blending at least part of the graphical element and at least part of one or more other graphical elements to produce a transformed graphical element. The transformed graphical element has an associated transformed type, and the transformed type is different than the original type. Information about the original type is stored, and the transformed graphical element, an adjacent graphical element, or both are processed using the stored information about the original type.

Abstract: Systems and methods provide a mechanism to print documents having transparent artwork that overlaps other artwork. One aspect of the systems and methods includes sending the document to a printer control system coupled to a printer. The printer control system detects overlapping areas, and processes the artwork into separate atomic regions. Objects contributing to the atomic region are placed in an object stack. A rasterizer having knowledge of the printer characteristics creates object raster buffers for the portions of the objects that contribute to the atomic region. The object raster buffers are then blended according to transparency values associated with the object to create an atomic region raster buffer. The atomic region raster buffer is combined with other atomic region raster buffers and raster images for other non-overlapping objects into a printer raster buffer that may be processed by the printer to produce a page.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for rendering an electronic document page that includes one or more objects. It is determined whether any object of the one or more objects on the document page is a transparent object. If a transparent object is found, the document page is divided into a plurality of subregions. For each subregion, a set of one or more opaque object components is generated for any object having a location in the subregion. The document page is rendered, including separately rendering each of the plurality of subregions.

Abstract: The invention features a method, system, and computer program product. A source bitmap image, a destination bitmap image, a source image feature outline surrounding a source region of the source bitmap image, and a destination image feature outline surrounding a destination region of the destination bitmap image are received. A point-to-point correspondence between the source image feature outline and the destination image feature outline is generated, such that the point-to-point correspondence defines a reshaping of the source image feature outline. An interpolation surface is calculated interpolating an area of the source bitmap image that includes the source region. The interpolation surface is reshaped using the point-to-point correspondence.

Abstract: Edges are detected in a raster image and generate parametric curves from the detected edges. The parametric curves are used to render a scaled version of the raster image. Some embodiments may allow edge locations within a raster image to retain a satisfactory level of sharpness when the raster image is scaled to a larger size.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.

Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.