Patents by Inventor Denis Foley
Denis Foley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11931522Abstract: A balloon guide catheter having a sleeved inflation lumen secured with a wire wrap for improved inflation lumen kink protection and a welded balloon construction provides a robust and flexible catheter with an exceptionally large inner lumen relative to its outer profile and enables rapid and reliable balloon inflation and deflation in a highly deliverable and kink resistant catheter. Balloon guide catheters having multiple sleeved inflation lumens and proximal luers for utilizing the multiple inflation lumens are also provided.Type: GrantFiled: October 14, 2019Date of Patent: March 19, 2024Assignee: NEURAVI LIMITEDInventors: Ronald Kelly, Michael Gilvarry, David Vale, Brendan Casey, Maeve Holian, Denis Foley
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Patent number: 11822491Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.Type: GrantFiled: October 20, 2021Date of Patent: November 21, 2023Assignee: NVIDIA CorporationInventors: John Feehrer, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
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Publication number: 20220043759Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.Type: ApplicationFiled: October 20, 2021Publication date: February 10, 2022Inventors: John FEEHRER, Denis FOLEY, Mark HUMMEL, Vyas VENKATARAMAN, Ram GUMMADI, Samuel H. DUNCAN, Glenn DEARTH, Brian KELLEHER
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Patent number: 11182309Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.Type: GrantFiled: November 4, 2019Date of Patent: November 23, 2021Assignee: NVIDIA CorporationInventors: John Feehrer, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
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Publication number: 20210133123Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.Type: ApplicationFiled: November 4, 2019Publication date: May 6, 2021Inventors: John FEEHRER, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
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Patent number: 10200154Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.Type: GrantFiled: June 23, 2017Date of Patent: February 5, 2019Assignee: Nvidia CorporationInventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
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Publication number: 20170288815Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.Type: ApplicationFiled: June 23, 2017Publication date: October 5, 2017Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
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Patent number: 9720768Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.Type: GrantFiled: October 6, 2015Date of Patent: August 1, 2017Assignee: Nvidia CorporationInventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
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Publication number: 20170097867Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.Type: ApplicationFiled: October 6, 2015Publication date: April 6, 2017Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
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Patent number: 8397079Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.Type: GrantFiled: June 4, 2008Date of Patent: March 12, 2013Assignee: ATI Technologies ULCInventors: Serag M. GadelRab, Bin Du, Zeeshan S. Syed, Denis Foley
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Patent number: 8156317Abstract: An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.Type: GrantFiled: May 16, 2008Date of Patent: April 10, 2012Assignee: ATI Technologies ULCInventors: James Lyall Esliger, Denis Foley
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Patent number: 8051312Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.Type: GrantFiled: May 20, 2008Date of Patent: November 1, 2011Assignee: Advanced Micro Devices, Inc.Inventor: Denis Foley
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Patent number: 8051345Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.Type: GrantFiled: June 4, 2008Date of Patent: November 1, 2011Assignee: ATI Technologies ULCInventors: Serag M. GadelRab, Bin Du, Zeeshan S. Syed, Denis Foley
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Publication number: 20100017893Abstract: A system includes a processing device, at least one data processing module, and a security control module. The security control module is operatively connected to both the processing device and the data processing module. The security control module is operative to control access to a protected register that is associated with the at least one data processing module. As such, the security control module operates as a firewall or filter to allow or deny access to a protected register. Security-unaware data processing module are therefore secured in the system at a central location while eliminating the need to use only security-aware data processing module. A method for securing data processing modules, including security-unaware data processing module, is also disclosed.Type: ApplicationFiled: July 21, 2008Publication date: January 21, 2010Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Denis Foley, Aris Balatsos
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Publication number: 20090307411Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Applicant: ATI TECHNOLOGIES ULCInventors: Serag M. GadelRab, Bin Du, Zeeshan S. Syed, Denis Foley
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Publication number: 20090307502Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Applicant: ATI TECHNOLOGIES ULCInventors: Serag M. GadelRab, Bin Du, Zeeshan S. Syed, Denis Foley
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Publication number: 20090289615Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.Type: ApplicationFiled: May 20, 2008Publication date: November 26, 2009Applicant: Advanced Micro Devices, Inc.Inventor: Denis Foley
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Publication number: 20090287895Abstract: A secure memory access system includes a memory control module, at least one direct memory access module, and a plurality of input/output interface modules. The direct memory access module is operative to transfer information between all of the input/output interface modules and the memory control module in response to transfer configuration information.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: Advanced Micro DevicesInventors: Denis Foley, Aris Balatsos
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Publication number: 20090285390Abstract: The various embodiments herein disclosed include a method wherein an integrated circuit (100) may receive a code image from an external device (127), encrypt the code image using a cryptographic logic (113) with a Hardware Unique Key to create a Hardware Unique Code Image (119) where the Hardware Unique Key is inaccessible to the external device (127). The integrated circuit (100) will then store the Hardware Unique Code Image wherein the Hardware Unique Code Image is executable only after decryption using the Hardware Unique Key. The method also includes sending a command to a cryptographic logic (113) to request decryption of the Hardware Unique Code Image by the cryptographic logic (113) using the Hardware Unique Key and executing the Hardware Unique Code Image by the boot software (103) after the decryption.Type: ApplicationFiled: May 16, 2008Publication date: November 19, 2009Applicant: ATI Technologies ULCInventors: Stefan Thomas Scherer, Denis Foley, Alwyn Dos Remedios
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Publication number: 20090288160Abstract: An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.Type: ApplicationFiled: May 16, 2008Publication date: November 19, 2009Applicant: ATI Technologies ULCInventors: James Lyall Esliger, Denis Foley