Patents by Inventor Dennis J. Ciplickas
Dennis J. Ciplickas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9793090Abstract: The present invention discloses an e-beam inspection tool, and an apparatus for detecting defects. In one aspect is described an apparatus for detecting defects that includes a focusing column that accelerates the e-beam and separately, for each of the plurality of predetermined locations, focuses the e-beam to a predetermined non-circular spot that is within the predetermined surface area of each of the plurality of predetermined locations based upon the major axis.Type: GrantFiled: January 6, 2016Date of Patent: October 17, 2017Assignee: PDF Solutions, Inc.Inventors: Indranil De, Christopher Hess, Dennis J. Ciplickas
-
Patent number: 9496119Abstract: The present invention discloses an e-beam inspection tool, and an apparatus for detecting defects. In one aspect is described an apparatus for detecting defects that includes a dual-deflection system that moves the e-beam over the integrated circuit to each of the plurality of predetermined locations, the dual deflection system including a magnetic deflection component that provides by magnetic deflection for movement of the e-beam through a plurality of areas on the integrated circuit and an electrostatic deflection component that provides by electrostatic deflection for movement of the e-beam within each of the plurality of areas.Type: GrantFiled: January 6, 2016Date of Patent: November 15, 2016Assignee: PDF Solutions, Inc.Inventors: Indranil De, Marian Mankos, Christopher Hess, Dennis J. Ciplickas
-
Publication number: 20160118217Abstract: The present invention discloses an e-beam inspection tool, and an apparatus for detecting defects.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Inventors: Indranil De, Christopher Hess, Dennis J. Ciplickas
-
Publication number: 20150270181Abstract: Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.Type: ApplicationFiled: February 3, 2015Publication date: September 24, 2015Inventors: Indranil De, Dennis J. Ciplickas, Stephen Lam, Jonathan Haigh, Vyacheslav V. Rovner, Christopher Hess, Tomasz W. Brozek, Andrzej J. Strojwas, Kelvin Doong, John K. Kibarian, Sherry F. Lee, Kimon W. Michaels, Marcin A. Strojwas, Conor O'Sullivan, Mehul Jain
-
Patent number: 7673262Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: May 13, 2008Date of Patent: March 2, 2010Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Publication number: 20080282210Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: ApplicationFiled: May 13, 2008Publication date: November 13, 2008Applicant: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7395518Abstract: A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may include clone test vehicle circuit patterns and/or clone test vehicle vias (1902). The presence of one or more defects (1904) in the one or more clone layers (1908) is an indicator of a tendency of the product circuit pattern to impact yield of a succeeding layer to be formed over the product circuit pattern in a product (1910).Type: GrantFiled: February 27, 2003Date of Patent: July 1, 2008Assignee: PDF Solutions, Inc.Inventors: Dennis J. Ciplickas, Christopher Hess
-
Patent number: 7373625Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: August 10, 2006Date of Patent: May 13, 2008Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7356800Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: August 10, 2006Date of Patent: April 8, 2008Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7348594Abstract: A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.Type: GrantFiled: August 30, 2002Date of Patent: March 25, 2008Assignee: PDF Solutions, Inc.Inventors: Dennis J. Ciplickas, Brian E. Stine, Yanwen Fei
-
Patent number: 7197726Abstract: A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (1000). Loop lines of the loop structure (1010) are connected on both sides of the NEST structure (1000).Type: GrantFiled: September 27, 2002Date of Patent: March 27, 2007Assignee: PDF Solutions, Inc.Inventors: Dennis J. Ciplickas, Markus Decker, Christopher Hess, Brian E. Stine, Larg H. Weiland
-
Patent number: 7174521Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: March 10, 2005Date of Patent: February 6, 2007Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7154115Abstract: A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the substrate. Each serpentine line has a plurality of turn sections that comprise two parallel line segments connected by a perpendicular line segment. Each of the plurality of test pads is connected to a respective turn section of a respective one of the nested serpentine lines. Each pair of test pads connected to one of the subset of the nested serpentine lines has at least a respectively different turn section portion connected therebetween.Type: GrantFiled: March 26, 2003Date of Patent: December 26, 2006Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, Larg H. Weiland, Dennis J. Ciplickas
-
Patent number: 7024642Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a . . . 301h, 302a . . . 302h), each pair of nested serpentine lines having a shared pad between them (312a . . . 312h).Type: GrantFiled: March 12, 2002Date of Patent: April 4, 2006Assignee: PDF Solutions, Inc.Inventors: Christopher Hess, David Stashower, Brian E. Stine, Larg H. Weiland, Richard Burch, Dennis J. Ciplickas
-
Patent number: 6901564Abstract: A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.Type: GrantFiled: July 18, 2002Date of Patent: May 31, 2005Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 6834375Abstract: A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit that controls the combinatorial logic circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial logic circuit element.Type: GrantFiled: September 16, 2002Date of Patent: December 21, 2004Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, Larg H. Weiland, Dennis J. Ciplickas, John Kibarian
-
Publication number: 20040232910Abstract: A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (1000). Loop lines of the loop structure (1010) are connected on both sides of the NEST structure (1000).Type: ApplicationFiled: July 16, 2004Publication date: November 25, 2004Inventors: Dennis J Ciplickas, Markus Decker, Christopher Hess, Brian E Stine, Larg H Weiland
-
Publication number: 20040094762Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a. . . 301h, 302a. . . 302h), each pair of nested serpentine lines having a shared pad between them (312a. . . 312h).Type: ApplicationFiled: September 12, 2003Publication date: May 20, 2004Inventors: Christopher Hess, David Stashower, Brian E. Stine, Larg H. Weiland, Richard Burch, Dennis J. Ciplickas
-
Publication number: 20030145292Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: ApplicationFiled: July 18, 2002Publication date: July 31, 2003Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower