OPPORTUNISTIC PLACEMENT OF IC TEST STRUCUTRES AND/OR E-BEAM TARGET PADS IN AREAS OTHERWISE USED FOR FILLER CELLS, TAP CELLS, DECAP CELLS, SCRIBE LINES, AND/OR DUMMY FILL, AS WELL AS PRODUCT IC CHIPS CONTAINING SAME

Abstract

Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 14/303,578, filed Jun. 12, 2014, which '578 application is a continuation-in-part of U.S. patent application Ser. No. 14/190,040, filed Feb. 25, 2014, which is a continuation-in-part of U.S. patent application Ser. No. 14/038,799, filed Sep. 27, 2013. This application also claims priority from the following Provisional U.S. Patent Applications: Ser. No. 61/942,163, filed Feb. 20, 2014; Ser. No. 61/971,306, filed Mar. 27, 2014; Ser. No. 61/972,787, filed Mar. 31, 2014; Ser. No. 61/982,652, filed Apr. 22, 2014; and Ser. No. 62/011,161, filed Mar. 12, 2014. Each of the '578, '040, '799, '163, '306, '787, '652 and '161 applications is incorporated by reference herein.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor integrated circuits and to methods for manufacturing and testing such circuits.

BACKGROUND OF THE INVENTION

Placement of “test structures” (defined herein as any patterning not required for circuit functioning, but designed, intended or used for monitoring or evaluation of the fabrication process or resultant partially or fully fabricated wafers/chips) on product wafers, has become commonplace over the last decade. Traditionally, such test structures are located in the scribe line areas between active die. See, e.g., Hess, Christopher, et al., “Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring,” IEEE International Conference on Microelectronic Test Structures, 2006.

U.S. Pat. No. 7,223,616 B2 (“Test Structures in Unused Areas of Semiconductor Integrated Circuits and Methods for Designing the Same”) to F. Duan, et al. describes the placement of interconnected, active test cells beneath the probe pads of test and product wafers.

U.S. Pat. No. 7,679,083 B2 (“Semiconductor integrated test structures for electron beam inspection of semiconductor wafers”) to S. Jansen, et al. describes the placement of test structures within large, pre-designated regions of product ICs.

While these and other known techniques that locate test structures on product wafers produce useful results, they are still less than ideal. Specifically, the area available in the scribe line of product wafers is strictly limited and can only accommodate certain types of test structures. Additionally, both the in-the-scribe-line and under-the-probe-pad methods suffer from the fact that the test structures are located far away from the most important active circuitry regions, and are thus not likely to accurately represent the processing environment of the active circuitry. Although the '083 patent can potentially mitigate this problem, it does so at the unacceptable cost of requiring large, dedicated test regions (see '083 patent, FIG. 5, regions 44-45) that consume otherwise precious active die area.

SUMMARY OF THE INVENTION

The present invention discloses several techniques for improving test structure coverage on product ICs with little or no sacrifice of active die area.

In accordance with one aspect of the invention, “filler cells” (defined as non-functional cells placed within the active circuitry region for the purpose of avoiding/relieving routing congestion and/or equalizing cell density) are replaced with self-contained test structures that do not require additional area or interconnect. Modern, standard-cell layouts commonly use such filler cells to relieve routing congestion. See, e.g., Cong, J., et al. “Optimizing routability in large-scale mixed-size placement,” ASP-DAC, 2013; and Menezes, C., et al. “Design of regular layouts to improve predictability,” Proceedings of the 6th IEEE International Caribbean Conference on Devices, Circuits and Systems, 2006. While PCT Applic. WO 2009/090516 A1 (“Monitor Cell and Monitor Cell Placement Method”) to C. Mayor, et al. proposes the idea of replacing a filler cell with a “monitor cell” (see FIG. 5, step 540), the proposed monitor cell is much too large to fit into a filler cell space and, even more importantly, requires additional interconnect for integration into a scan chain. Examples of test-enabled filler (Fill) cells suitable for use in connection with the invention are disclosed in the '163 provisional application, and in FIGS. 11-32 of this application.

In accordance with another aspect of the invention, decap (decoupling capacitance) cells are modified to incorporate one or more self-contained test structures. Use of such decap cells is well known in the art. See, e.g., X. Meng, et al., “Novel Decoupling Capacitor Designs for sub-90 nm CMOS Technology,” Proceedings of the 7th IEEE International Symposium on Quality Electronic Design, 2006.

In accordance with another aspect of the invention, well tap (tap) cells are modified to incorporate one or more self-contained test structures. Use of such tap cells is well known in the art. See, e.g., U.S. Pat. No. 6,388,315 (“Tap connections for circuits with leakage suppression capability”), incorporated by reference herein; Jungeblut, T., et al., 2010, “A modular design flow for very large design space exploration,” at FIG. 4 (“- add well tap cells”). Examples of such test-enabled tap cells are disclosed in the '163 provisional application.

In accordance with still another aspect of the invention, “dummy fill” areas (see U.S. Pat. No. 7,137,092 B2, incorporated by reference herein) are populated with test structure patterns.

U.S. Pat. No. 7,217,579 (“Voltage contrast test structure”) and U.S. Pat. No. 7,679,083 (“Semiconductor integrated test structures for electron beam inspection of semiconductor wafers”), both incorporated by reference herein, disclose the use of voltage contrast test structures in the scribe line areas of semiconductor wafers. Another aspect of the present invention involves the use of scribe line areas for additional test structure insertion. Such scribe line areas can be advantageously used to implement test structures whose use might be discouraged or prohibited within the active die areas of product wafers, either because of actual performance issues or requirements for compatibility with existing DRC (design rule checking) flows. Examples of such discouraged/prohibited test structures include structures that involve intentional inter-layer misalignment(s), sub-design rule or canary structures, or structures whose density or patterning is incompatible with requirements in the active die area. See, for example, abandoned U.S. Patent Applic. No. 2009-0102501 A1 (“Test structures for e-beam testing of systematic and random defects in integrated circuits”), incorporated herein by reference, for examples of e-beam compatible canary test structures. In certain embodiments of this invention, inter-die scribe line areas of the inventive product IC wafers are entirely or mostly populated with voltage contrast test structures whose use within the active die areas would be discouraged or prohibited.

Another aspect of the invention involves the opportunistic insertion of test pads (a type of “test structure,” as hereinabove defined) into the dummy fill, filler cell, decap cell, and/or tap cell positions noted above (and/or within such cells). Such test pads preferably comprise charged particle (e.g., e-beam) targets, preferably sized in the smaller dimension to be in the range of 1× to 10× of the minimum resolvable feature size at a given technology node, but may also comprise micro- or nano-probeable contact pads. Such test pads may be positioned above associated test structures, adjacent to associated test structures, connected to non-adjacent test structures on the same layer, or connected to associated test structures on lower layer(s).

Other aspects of the invention relate to ICs and IC layouts having one, two, three, or four of the above-noted types of opportunistically inserted test structures, either with or without the traditional scribe-line and under-the-pad test structures. Still further aspects of the invention relate to CAD methods for forming such IC layouts, to fabrication process that utilize, at least in part, information obtained from the inventive, opportunistically inserted test structures, and to ICs manufactured thereby.

Accordingly, generally speaking, and without intending to be limiting, certain aspects of the invention relate to product ICs that contain, for example: at least ten, twenty, thirty, or more rows of at least fifty, seventy-five, one-hundred or more abutting cells; characterized in that: each of the rows includes a plurality of logic cells; and at least half, three-quarters or more of the rows include a test structure in a filler, decap, or tap cell position (and/or within such cells). Such product ICs may additionally contain a plurality of dummy fill test structures (including, but not limited to, test pads) implemented in dummy fill regions that at least partially overlay the rows. Such dummy fill test structures may appear on any patterned layer and, in particular, on one, or more than one metal layer.

Each of the test structures is preferably self-contained, thereby not requiring use of routing areas for on-chip connections. In other words, in accordance with this self-contained aspect of the invention, replacing the filler/decap/tap cells with the inventive test cells/structures should not affect the available routing areas. In some embodiments, such self-contained test structures may be formed in the footprints of multiple, adjacent filler, decap, or tap cells, thus allowing even larger and/or irregularly shaped self-contained test structures. Such product ICs may contain test structures that are configured for e-beam testing, test structures that are configured for SEM inspection, test structures that are configured for bright field inspection, test structures that are configured for probe contacting (by microprobe, nanoprobe or probe card), or any combination of two, three, or four of these.

Again, generally speaking, and without intending to be limiting, other aspects of the invention relate to product ICs that contain, for example: a contiguous region containing at least twenty, thirty, forty, or more adjacent rows of at least one-hundred, one-hundred-fifty, two-hundred or more abutting cells, with routing areas; characterized in that: each of the rows includes a majority (or a super-majority, such as 60%, 70%, or 80%) of logic cells; and the contiguous region also contains at least twenty-five (or 50, 100, 150, or more) irregularly distributed, self-contained test structures, each positioned in one of the rows, in a position otherwise suitable for a logic cell, or a filler cell, or a tap cell. In some embodiments, at least some of the test structures are contained within decap cells. Such product ICs may also include a plurality of self-contained, dummy fill test structures, each at least partially overlying the contiguous region, but not connected to any of the logic cells (excluding connections to common power nets). In some embodiments, such dummy fill test structures may occupy more than one interconnect layer. In some embodiments, at least some of said test structures are canary (i.e., sub-Design Rule) test structures, and at least some of the dummy fill test structures are random defect test structures. In other embodiments, test structures may comprise DR-compliant structures configured to test for, or evaluate, systematic failure modes. And embodiments that comprise combinations of these are contemplated as well.

Again, generally speaking, and without intending to be limiting, other aspects of the invention relate to IC fabrication processes that include, for example, at least the steps of: subjecting an IC wafer to initial fabrication steps; obtaining measurements from at least five (or 10, 20, 40 or more) self-contained test structures, opportunistically distributed within a contiguous logic portion of the wafer; and, based at least in part, on measurements obtained from the test structures, selectively subjecting the wafer to additional and/or modified fabrication steps. In certain embodiments, obtaining measurements may involve exciting the test structures by charged particles (such as by e-beam), inspecting the test structures by bright field inspection, inspecting the test structures by SEM inspection, or contacting the test structures by probing for electrical measurement. In certain embodiments, selectively subjecting the wafer to additional fabrication steps or Physical Failure Analysis may involve determining whether to rework one or more of the initial fabrication steps, or determining whether or not to perform the additional fabrication steps, or discard the wafer.

Again, generally speaking, and without intending to be limiting, a process for making a product IC wafer, in accordance with certain embodiments of the invention, may illustratively comprise at least the following steps: obtaining an initial product wafer layout; using a computer to analyze the initial product wafer layout and identify areas of opportunity (e.g., dummy fill, filler cells, tap cells, decap cells) for test structure insertion; using the computer to modify the initial product wafer layout by inserting a plurality of test structures that collectively make up at least one distributed DOE across the areas of opportunity identified for test structure insertion; storing information necessary to fabricate the modified product wafer layout, but not information needed to utilize the distributed DOE(s), in a computer-readable layout data record; storing information needed to utilize the distributed DOE(s) in a computer-readable test data record; and, providing information from the layout data record to a fabricator in order to enable fabrication of a wafer based on the modified product wafer layout. In accordance with this, and other, aspects of the invention, such layout modifications can proceed either during the design flow (i.e., before design sign-off) or during a subsequent mask data processing (MDP) step(s), or during both. In accordance with a related aspect of the invention, a method for making IC product chips may illustratively comprise at least the following steps: receiving a first product IC wafer comprising multiple product IC dies with embedded test structures that collectively make up at least one distributed DOE; receiving data that identifies and enables use of at least one of the distributed DOE(s); utilizing the at least one distributed DOE(s) to obtain information concerning the fabrication of the first product IC wafer; and, processing the first product IC wafer into multiple IC product chips. Such methods may further comprise at least the following additional steps: receiving a second product IC wafer identical to the first product IC wafer; utilizing at least one of the distributed DOE(s) on the second product IC wafer to obtain information concerning the fabrication of the second product IC wafer; and, processing the second product IC wafer into multiple IC product chips. In accordance with these aspects of the invention, data from such DOE(s) and/or test structure(s) may be utilized in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.

Again, generally speaking, and without intending to be limiting, a product IC wafer, in accordance with another aspect of the invention, may comprise at least: an area of functional product circuitry, with a multiplicity of e-beam exercisable test structures (or pads/targets) distributed within the area of functional product circuitry; and, a plurality of e-beam skip zones, each of which allows an e-beam scanner to skip at least 10%, 15%, or 20% of its overall scan length (measured in the scan direction) without missing the opportunity to exercise any test structures (or pads/targets). Such product IC wafers may preferably further include at least: one or more empty e-beam scanning tracks, each spanning the entire width of the area of functional product circuitry.

Again, generally speaking, and without intending to be limiting, another aspect of the invention relates to product wafers that contain, for example, at least the following: an array of at least three-by-three (or five-by-five, ten-by-ten, twenty-by-twenty, or fifty-by-fifty, etc.) product die, with scribe line areas separating the product die; with the wafers characterized in that: each of the product dies includes a (large) plurality of operable (combinational and/or sequential) logic cells that support product functionality; each of the product dies includes a plurality of test-enabled tap cells, interspersed with the logic cells, wherein each of the test-enabled tap cells comprises a self-contained voltage contrast test structure (with or without an e-beam test pad); and, each of the scribe line areas contains a plurality of voltage contrast test structures (with or without corresponding e-beam test pads). Such product dies may further include: a plurality of test-enabled decap cells, wherein each of the test-enabled decap cells comprises a self-contained voltage contrast test structure (with or without corresponding e-beam test pads); a plurality of test-enabled filler cells, wherein each of the test-enabled filler cells comprises a self-contained voltage contrast test structure (with or without corresponding e-beam test pads); and/or a plurality of self-contained voltage contrast test structures implemented in dummy fill regions of said product dies (with or without corresponding e-beam test pads). In certain embodiments, the scribe line areas are substantially fully populated with voltage contrast test structures (including e-beam target pads), and some or a majority of the test structures contained in the scribe line areas may comprise canary structures, contain intentional layer misalignments, and/or contain intentional violations of process design rules.

Again, generally speaking, and without intending to be limiting, another aspect of the invention relates to IC fabrication processes that comprise, for example, at least the following steps: subjecting a product IC wafer to initial fabrication steps; obtaining e-beam excited measurements from at least forty (preferably, at least one hundred) self-contained test structures, at least twenty of the test structures irregularly distributed within a contiguous logic portion of the wafer (i.e., portion of the wafer that contains functional product logic), and at least twenty of the test structures located within scribe line portions of the wafer; and, based, at least in part, on measurements obtained from the test structures, selectively subjecting the wafer to additional fabrication steps. In certain preferred embodiments, obtaining measurements comprises selectively targeting e-beam target pads located in the scribe line areas of the wafer, without continuously scanning any substantial portion of the wafer (by, for example, sampling a single pixel value, or fewer than ten pixel values). In certain preferred embodiments, obtaining measurements comprises selectively targeting e-beam target pads located within the contiguous logic portion of the wafer, without continuously scanning any substantial portion of the wafer. In some embodiments, selectively subjecting may include determining whether to rework one or more of the initial fabrication steps. And in some embodiments, selectively subjecting may include determining whether or not to perform the additional fabrication steps.

Certain embodiments of the invention may include electrically probeable test structures, including but not limited to the type described in the '652 provisional application, located in the scribe line regions of product wafers. Such electrically probeable test structures may include their own probe pads, or may share one or more pads with nearby voltage-contrast test structures, thereby allowing single pads to function both as a probe pads and e-beam target pads.

In the discussion that follows, the inventive cells (of FIGS. 11-85, below) are referenced as both “cells” and “means.” For clarity and definiteness, it is applicants' intent that a reference to, for example, “a FIG. 82 cell” be construed to mean “a cell having the topological design depicted in FIG. 82,” whereas a similar reference to “a FIG. 82 means” be construed, under §112 ¶6, to cover “a cell that implements the logic function of the FIG. 82 cell, i.e., ‘a two-input, tri-state multiplexor in drive strength 1’ and has the structure depicted in FIG. 82, or an equivalent structure.”

Generally speaking, and without intending to be limiting, additional aspects of the invention relate to product integrated circuits that contain, within a contiguous logic region of at least 500 (or 1000, 1500, etc.) cells, (i) at least a select number (e.g., three, four, five, six, seven, etc.) of distinct functional cells selected from the set consisting of: a FIG. 33A-B cell; a FIG. 34A-B cell; a FIG. 35A-B cell; a FIG. 36A-B cell; a FIG. 37A-B cell; a FIG. 38A-B cell; a FIG. 39A-B cell; a FIG. 40A-B cell; a FI. G41A-B cell; a FIG. 42A-B cell; a FIG. 43A-B cell; a FIG. 44A-B cell; a FIG. 45 cell; a FIG. 46 cell; a FIG. 47 cell; a FIG. 48 cell; a FIG. 49 cell; a FIG. 50 cell; a FIG. 51 cell; a FIG. 52 cell; a FIG. 53 cell; a FIG. , 54 cell; a FIG. 55 cell; a FIG. 56 cell; a FIG. 57 cell; a FIG. 58 cell; a FIG. 59 cell; a FIG. 60 cell; a FIG. 61 cell; a FIG. 62 cell; a FIG. 63 cell; a FIG. 64 cell; a FIG. 65 cell; a FIG. 66 cell; a FIG. 67 cell; a FIG. 68 cell; a FIG. 69 cell; a FIG. 70 cell; a FIG. 71 cell; a FIG. 72 cell; a FIG. 73 cell; a FIG. 74 cell; a FIG. 75 cell; a FIG. 76 cell; a FIG. 77 cell; a FIG. 78 cell; a FIG. 79 cell; a FIG. 80 cell; a FIG. 81 cell; a FIG. 82 cell; a FIG. 83A-B cell; a FIG. 84 cell; and, a FIG. 85 cell; and (ii) at least ten test-enabled cells, including at least one (or two, three, four, etc.) distinct types, with the at least ten test-enabled cells selected from the set consisting of: a FIG. 11 cell; a FIG. 12 cell; a FIG. 13 cell; a FIG. 14 cell; a FIG. 15 cell; a FIG. 16 cell; a FIG. , 17 cell; a FIG. 18 cell; a FIG. 19 cell; a FIG. 20 cell; a FIG. 21 cell; a FIG. 22 cell; a FIG. 23 cell; a FIG. 24 cell; a FIG. 25 cell; a FIG. 26 cell; a FIG. 27 cell; a FIG. 28 cell; a FIG. 29 cell; a FIG. 30 cell; a FIG. 31 cell; and, a FIG. 32 cell. Another aspect of the invention relates to methods for making such ICs by, for example, instantiating and fabricating at least a select number of distinct cells selected from the aforesaid sets.

Again, Generally speaking, and without intending to be limiting, additional aspects of the invention relate to product integrated circuits that contain, within a contiguous logic region of at least 200 (or 500, 1000, etc.) means, (i) at least a select number (2, 3, 4, 5, etc.) of distinct “means” (i.e., the corresponding means or the §112 ¶6 “equivalent thereof”) selected from the set consisting of: a FIG. 33A-B means; a FIG. 34A-B means; a FIG. 35A-B means; a FIG. 36A-B means; a FIG. 37A-B means; a FIG. 38A-B means; a FIG. 39A-B means; a FIG. 40A-B means; a FIG. 41A-B means; a FIG. 42A-B means; a FIG. 43A-B means; a FIG. 44A-B means; a FIG. 45 means; a FIG. 46 means; a FIG. 47 means; a FIG. 48 means; a FIG. 49 means; a FIG. 50 means; a FIG. 51 means; a FIG. 52 means; a FIG. 53 means; a FIG. 54 means; a FIG. 55 means; a FIG. 56 means; a FIG. 57 means; a FIG. 58 means; a FIG. 59 means; a FIG. 60 means; a FIG. 61 means; a FIG. 62 means; a FIG. 63 means; a FIG. 64 means; a FIG. 65 means; a FIG. 66 means; a FIG. 67 means; a FIG. 68 means; a FIG. 69 means; a FIG. 70 means; a FIG. 71 means; a FIG. 72 means; a FIG. 73 means; a FIG. 74 means; a FIG. 75 means; a FIG. 76 means; a FIG. 77 means; a FIG. 78 means; a FIG. 79 means; a FIG. 80 means; a FIG. 81 means; a FIG. 82 means; a FIG. 83A-B means; a FIG. 84 means; and, a FIG. 85 means; and (ii) at least ten test-enabled “means,” including at least one (or two, three, four, etc.) distinct types, with the at least ten test-enabled means selected from the set consisting of: a FIG. 11 means; a FIG. 12 means; a FIG. 13 means; a FIG. 14 means; a FIG. 15 means; a FIG. 16 means; a FIG. 17 means; a FIG. 18 means; a FIG. 19 means; a FIG. 20 means; a FIG. 21 means; a FIG. 22 means; a FIG. 23 means; a FIG. 24 means; a FIG. 25 means; a FIG. 26 means; a FIG. 27 means; a FIG. 28 means; a FIG. 29 means; a FIG. 30 means; a FIG. 31 means; and, a FIG. 32 means. Another aspect of the invention relates to methods for making such ICs by, for example, instantiating and fabricating at least a select number of distinct means selected from the aforesaid sets. Further aspects of the invention relate to electronic systems (fixed or portable) that include at least a selected number (e.g., one, two, three, four) of the ICs of the type defined above, as well as other optional components, such as rechargeable power source(s). And still further aspects of the invention relate to methods for making such ICs by, for example, instantiating at least selected numbers of said above-referenced “cells” and/or “means.”

While the exemplary logic and test-enabled cells (FIGS. 11-85) have avoided the use of tapered devices to avoid the parametric variability problems and functional yield loss problems associated such devices, persons skilled in the art will immediately appreciate that equivalent, alternative versions of these cells may employ tapered devices, and that such alternative, tapered versions are within the scope of this invention.

Another aspect of this invention relates to the use of a tool using a charged particle column (electrons or ions), whose primary function is to find defects on the surface of semiconductor wafers (i.e., function as an inspector). (While the present description uses the term “e-beam,” it is understood that it applies to all charged beams.)

In accordance with one aspect of the invention, we describe a VC inspector that samples pixels on a wafer surface. This method of scanning is fundamentally different from all inspectors designed before. In one embodiment, the pixels have certain designated X-Y coordinates whose pixel value (i.e., electron beam signal) is used to determine if a defect exists or not. This can be viewed as a 0-D inspection, instead of the typical 2-D inspection of the prior art.

In one embodiment, the pixel corresponds to a “pad” in an electrical test structure that is specifically created for the purpose finding a voltage contrast defect. The beam shines on the pad for a designated length of time. Each test structure may have one or more pads (inspector reads out one pixel per pad). Such test pads may exist on a semiconductor wafer whose patterns have been designed primarily as a “test chip,” or may be embedded in a “product wafer.”

In one embodiment, each pixel corresponds to a certain specific location of a semiconductor product layout. These pixels are selected because a signal abnormality at these locations on the product are indicative of a specific type or types of defect.

In one embodiment, the stage is held stationary akin to “step and scan” inspection. Once the pixel values corresponding to a given field of view are sensed, the stage moves to another location where the next set of pixels can be read out.

In one embodiment, the stage is moving when the pixels are being scanned and the inspection happens by deflecting the e-beam accordingly to account for the motion of the stage.

In one embodiment, the duration of the pixel readout at each location is dynamic with respect to each pixel, i.e., depending on the test structure or product circuit being inspected at each point, the duration of the beam hold at the location is changed suitably.

In one embodiment, the size of the beam on the wafer is not fixed, but is changed dynamically for each location being read out. This type of beam shaping is similar to what is used in e-beam writers. The sizing of the spot on a per structure basis allows the beam to be optimized with respect to each structure. The optimization is typically to maximize the signal-to-noise ratio of the inspection. Another aspect of the invention relates to design of a voltage-contrast device-under-test (“VC DUT”), with a test pad, where the complete structure is tested with very few pixels (<10). Such a VC DUT may have a test pad whose size and shape accommodates non-circular incident e-beams, while maximizing SNR at the same time. Such beams may also be square shaped to match pads that are similarly square shaped. Such pads may be configured to capture beams with an asymmetric aspect ratio (X/Y length ratio) that is greater than 3 (e.g., DUT with an X-dimension of 100 nm and Y dimension 300-600 nm would have aspect ratio of 3:1, 4:1, 5:1).

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other, aspects, features and advantages of the present invention are exemplified in the following set of drawings, in which:

FIG. 1 conceptually depicts an illustrative section of a standard cell layout that includes logic cells (L), filler cells (F), and tap cells (T) arranged in rows, with routing areas between the rows, and nearby decap cells (dC);

FIG. 2 depicts the same layout as FIG. 1, but with dummy fill areas indicated in a first layer;

FIG. 3 depicts the same layout as FIGS. 1-2, but with dummy fill area(s) indicated in a second layer;

FIG. 4 depicts an exemplary layout in accordance with the invention, in which the filler cells, tap cells, decap cells, and dummy fill regions of the FIG. 3 layout are replaced by self-contained test structures;

FIG. 5 conceptually depicts a preferred form of standard cell layout (for use in accordance with the invention);

FIG. 6 depicts an exemplary layout in accordance with the invention, in which the filler cells, decap cells, tap cells, and dummy fill regions of the FIG. 5 layout are replaced by self-contained test structures;

FIG. 7 depicts an exemplary process flow for opportunistic test structure insertion in accordance with certain embodiments of the invention;

FIG. 8 depicts an exemplary process flow for utilizing the opportunistically inserted test structures (as per FIG. 7 or 10) to generate useful results;

FIG. 9 conceptually depicts a portion of an exemplary wafer or die, showing the opportunistically inserted test pads and/or structures arranged to produce empty track(s) and/or skip zone(s) that enable faster e-beam scanning;

FIG. 10 depicts an alternative exemplary process flow for opportunistic test structure insertion in accordance with certain embodiments of the invention;

FIG. 11 depicts a first exemplary test-enabled tap cell;

FIG. 12 depicts a first exemplary test-enabled filler cell;

FIG. 13 depicts another exemplary test-enabled filler cell;

FIG. 14 depicts another exemplary test-enabled tap cell;

FIG. 15 depicts another exemplary test-enabled filler cell;

FIG. 16 depicts another exemplary test-enabled tap cell;

FIG. 17 depicts another exemplary test-enabled filler cell;

FIG. 18 depicts another exemplary test-enabled filler cell;

FIG. 19 depicts another exemplary test-enabled tap cell;

FIG. 20 depicts another exemplary test-enabled filler cell;

FIG. 21 depicts another exemplary test-enabled filler cell;

FIG. 22 depicts another exemplary test-enabled filler cell;

FIG. 23 depicts another exemplary test-enabled tap cell;

FIG. 24 depicts another exemplary test-enabled filler cell;

FIG. 25 depicts another exemplary test-enabled tap cell;

FIG. 26 depicts another exemplary test-enabled filler cell;

FIG. 27 depicts another exemplary test-enabled tap cell;

FIG. 28 depicts another exemplary test-enabled filler cell;

FIG. 29 depicts another exemplary test-enabled tap cell;

FIG. 30 depicts another exemplary test-enabled tap cell;

FIG. 31 depicts another exemplary test-enabled filler cell;

FIG. 32 depicts another exemplary test-enabled filler cell;

FIGS. 33A-85 depict exemplary cells from an exemplary standard cell library; in particular, FIGS. 33A-B respectively depict abutting left and right portions of a first exemplary standard cell;

FIGS. 34A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 35A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 36A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 37A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 38A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 39A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 40A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 41A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 42A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 43A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIGS. 44A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIG. 45 depicts another exemplary standard cell;

FIG. 46 depicts another exemplary standard cell;

FIG. 47 depicts another exemplary standard cell;

FIG. 48 depicts another exemplary standard cell;

FIG. 49 depicts another exemplary standard cell;

FIG. 50 depicts another exemplary standard cell;

FIG. 51 depicts another exemplary standard cell;

FIG. 52 depicts another exemplary standard cell;

FIG. 53 depicts another exemplary standard cell;

FIG. 54 depicts another exemplary standard cell;

FIG. 55 depicts another exemplary standard cell;

FIG. 56 depicts another exemplary standard cell;

FIG. 57 depicts another exemplary standard cell;

FIG. 58 depicts another exemplary standard cell;

FIG. 59 depicts another exemplary standard cell;

FIG. 60 depicts another exemplary standard cell;

FIG. 61 depicts another exemplary standard cell;

FIG. 62 depicts another exemplary standard cell;

FIG. 63 depicts another exemplary standard cell;

FIG. 64 depicts another exemplary standard cell;

FIG. 65 depicts another exemplary standard cell;

FIG. 66 depicts another exemplary standard cell;

FIG. 67 depicts another exemplary standard cell;

FIG. 68 depicts another exemplary standard cell;

FIG. 69 depicts another exemplary standard cell;

FIG. 70 depicts another exemplary standard cell;

FIG. 71 depicts another exemplary standard cell;

FIG. 72 depicts another exemplary standard cell;

FIG. 73 depicts another exemplary standard cell;

FIG. 74 depicts another exemplary standard cell;

FIG. 75 depicts another exemplary standard cell;

FIG. 76 depicts another exemplary standard cell;

FIG. 77 depicts another exemplary standard cell;

FIG. 78 depicts another exemplary standard cell;

FIG. 79 depicts another exemplary standard cell;

FIG. 80 depicts another exemplary standard cell;

FIG. 81 depicts another exemplary standard cell;

FIG. 82 depicts another exemplary standard cell;

FIGS. 83A-B respectively depict abutting left and right portions of another exemplary standard cell;

FIG. 84 depicts another exemplary standard cell;

FIG. 85 depicts another exemplary standard cell;

FIG. 86 depicts the prior-art “step and scan” and “swathing” techniques;

FIG. 87 depicts a prior-art beam scanning/shaping apparatus;

FIG. 88 shows examples of the beam shapes that can be realized using the column of FIG. 87;

FIG. 89 depicts an exemplary semiconductor wafer that is typically circular and broken up into identical dies, and further depicts an example case where all of the test structures are located in the scribe areas of the die;

FIG. 90 illustrates a series of test structures laid out with their pads in a column, where a spot of the electron beam scans over the pads by the relative motion of the wafer to the spot;

FIG. 91 shows an illustration of an electron spot shaped in a non-circular manner to match the size and shape of the pad, so as to maximize the electron current that is delivered to the pad;

FIG. 92 shows an illustration of pad shapes being sized according to the amount of charge that needs to be delivered to the test structures, wherein test structures needing more charge have longer pads along the scanning direction of the beam to increase the beam dwell time on the pad;

FIG. 93 depicts a scenario in which the beam moves fast if there is a long stretch with no pads to charge, but with constant velocity and slower in populated regions to allow more charging of the pads of the test structures;

FIG. 94 shows test structures laid out on either sides of the pads, which allows a larger number of test structures to be scanned with a single pass of the beam on the wafer;

FIG. 95 shows how solid pads may be split into finer lines or alternate shapes so that their layout will be compatible with the design rules of the semiconductor process;

FIG. 96 depicts “net grey” pads for use with certain embodiments of the invention;

FIG. 97 conceptually illustrates one embodiment of a VC DUT in accordance with certain aspects/embodiments of the invention;

FIG. 98 conceptually illustrates another embodiment of a VC DUT in accordance with certain aspects/embodiments of the invention; and,

FIG. 99 conceptually illustrates another embodiment of a VC DUT in accordance with certain aspects/embodiments of the invention.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 conceptually depicts an illustrative section of a prior-art standard cell layout that includes logic cells (L), tap cells (T) and filler cells (F) arranged in rows, with routing channels between the rows, and nearby decap cells (dC). As depicted, the overall distribution of decap, tap and filler cells within this illustrative section is irregular and does not follow any obvious pattern or symmetry. (Persons skilled in the art will immediately recognize that the depictions herein are conceptual, and only intended to illustrate the principles of the invention, rather than represent actual layout realities. Indeed, such skilled artisans will appreciate that tap cells typically come in only one size and appear at regular or nearly regular intervals. Similarly, such skilled artisans will also recognize that decap cells can, and frequently are, sized to fit within and placed within the standard cell rows.)

FIG. 2 conceptually depicts the same prior-art layout as FIG. 1, but with dummy fill areas indicated in a first layer. These dummy fill areas are shown as diagonally hashed areas, and, as depicted, may be regularly (e.g., rectangular) or irregularly shaped. Dummy fill areas most useful in accordance with the invention typically appear on the third and above metal layers (e.g., M3, M4, M5, M6), but may also appear on lower metal and/or previous layers such as active, poly layer(s), or local interconnect. (As persons skilled in the art will appreciate, the depiction of dummy fill in FIG. 2 is conceptual, since dummy fill areas would typically be much larger in area than one or a few standard cells.)

FIG. 3 conceptually depicts the same layout as FIGS. 1-2, but with dummy fill area(s) indicated in a second layer. This second-layer dummy fill area is shown in the scale pattern hashing.

FIG. 4 conceptually depicts an exemplary layout, based on that of FIG. 3, that illustrates certain aspects of the present invention. As exemplified in FIG. 4, filler cells (F) and tap cells (T) have been replaced by test structures (TS4, TS5, TS6, TS7, TS8, TS9, TS10), decap cells (dC) have been replaced by test-enabled decap cells (dC-T), and dummy fill regions have been replaced by test structures (TS1, TS2, TS3).

FIG. 5 conceptually depicts a preferred form of standard cell layout, suitable for use in accordance with the invention. This figure depicts the more modern style, in which cell rows are abutting and routing areas are over-the-cells. Though not depicted, it should be understood that routing areas need not be regularly shaped, nor need they be oriented in a direction parallel to the rows.

FIG. 6 depicts an exemplary layout in accordance with the invention, in which the filler cells (F), tap cells (T), decap cells (dC), and dummy fill (diagonally hashed) regions of the FIG. 5 layout are replaced by self-contained test structures (TS, dC-T, and dotted region, respectively).

As persons skilled in the art will recognize, numerous options exist for the selection of particular test structures to be opportunistically instantiated in accordance with the present invention.

Product ICs in accordance with the invention may include test structures adapted for in-line systematic defect inspection, by bright field and/or e-beam (or other charging), of product layout patterns most susceptible to systematic defects, including multi-patterning structures. Such test structures preferably include canary structures (i.e., sub-design rule structures used to explore process-layout marginalities).

Product ICs in accordance with the invention may also include test structures adapted for in-line random defect inspection, by bright field and e-beam tools, of product-like patterns for the most likely defects, such as single line opens and most likely via open locations (including canary structures).

Product ICs in accordance with the invention may also include test structures adapted for in-line metrology, such as structures to extract overlay/misalignment, product-specific patterns for poly CD, MOL CD, via bottom CD, metal CD and height, dielectric heights, etc., and may be testable electrically and/or by Scanning Electron Microscope (e.g., for overlay, line CD and profile).

Product ICs in accordance with the invention may also include Physical Failure Analysis (PFA) structures for likely systematic defects, where such PFAs may include product specific layout patterns (including canary structures) and pads for probing.

And product ICs in accordance with the invention may also include any combination of the above-noted, or other, usable test structures.

For test-enabled decap cells, the preferred test structures are M1 structures for Single Line Open inspection.

Important goals for the design of test structures in accordance with certain embodiments of the invention are that: (1) test structures should not affect printability of the active geometry (i.e., standard cells or interconnect), and/or (2) test structures should be representative of the active cell properties (printability and electrical characteristics).

FIGS. 11-32, as described in detail below, depict an exemplary set of VC DUTs, suitable for use in certain embodiments of the invention.

Reference is now made to FIG. 11, which depicts a first exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Merged Via configuration short to neighboring metal/local interconnect. In the depicted configuration, a passing response=floating metal =dark pad, whereas a failing response=short to grounded underlying metal→grounded pad=bright pad. (Persons skilled in the art will appreciate that e-beam inspection can be configured to produce either a dark or a bright condition for floating polygons. While the latter configuration is typically more stable, and hence is assumed for the examples in this disclosure, persons skilled in the art will appreciate that the present invention is useful in either configuration.)

Reference is now made to FIG. 12, which depicts a first exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Merged Via configuration short to underlying metal. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying metal→grounded pad=bright pad.

Reference is now made to FIG. 13, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Merged Via configuration short to underlying metal. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying metal→grounded pad=bright pad.

Reference is now made to FIG. 14, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Merged via configuration open. In the depicted configuration, a passing response=grounded metal=bright pad, whereas a failing response=failed connection to grounded underlying metal→floating pad=dark pad.

Reference is now made to FIG. 15, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Merged via configuration open. In the depicted configuration, a passing response=grounded metal=bright pad, whereas a failing response=failed connection to grounded underlying metal→floating pad=dark pad.

Reference is now made to FIG. 16, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Via short to neighboring metal/local interconnect. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying metal→grounded pad=bright pad.

Reference is now made to FIG. 17, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Via short to underlying metal. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying metal→grounded pad=bright pad.

Reference is now made to FIG. 18, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Via short to underlying metal. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying metal→grounded pad=bright pad.

Reference is now made to FIG. 19, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Contact short to underlying layer. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying layer→grounded pad=bright pad.

Reference is now made to FIG. 20, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Contact short to underlying layer. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying layer→grounded pad=bright pad.

Reference is now made to FIG. 21, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Contact short to underlying layer. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying layer→grounded pad=bright pad.

Reference is now made to FIG. 22, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Contact short to underlying layer. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded underlying layer→grounded pad=bright pad.

Reference is now made to FIG. 23, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: same color Metal End to Metal Side short. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded metal layer→grounded pad=bright pad.

Reference is now made to FIG. 24, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: same color Metal End to Metal Side short. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded metal layer→grounded pad=bright pad.

Reference is now made to FIG. 25, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Metal open. In the depicted configuration, a passing response=grounded metal =bright pad, whereas a failing response=connection to grounded metal fails→floating pad=dark pad.

Reference is now made to FIG. 26, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Metal open. In the depicted configuration, a passing response: grounded metal=bright pad, whereas a failing response=connection to ground metal fails→floating pad=dark pad.

Reference is now made to FIG. 27, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Metal short to Metal corner. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded metal layer→grounded pad=bright pad.

Reference is now made to FIG. 28, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Metal short to Metal corner. In the depicted configuration, a passing response=floating metal=dark pad, whereas a failing response=short to grounded metal layer→grounded pad=bright pad.

Reference is now made to FIG. 29, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: same color Contact end to Contact short. In the depicted configuration, a passing response=floating contacts=dark pad, whereas a failing response=short to grounded contact layer→grounded pad=bright pad.

Reference is now made to FIG. 30, which depicts another exemplary test-enabled tap cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: different color Contact to Contact end short. In the depicted configuration, a passing response=floating contacts=dark pad, whereas a failing response=short to grounded contact layer→grounded pad=bright pad.

Reference is now made to FIG. 31, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Contact to Contact Short. In the depicted configuration, a passing response=floating contacts=dark pad, whereas a failing response=short to grounded contact layer→grounded pad=bright pad.

Reference is now made to FIG. 32, which depicts another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad, and is configured for e-beam (or other charged particle) inline testing to detect the following failure mode: Contact to Contact Short. In the depicted configuration, a passing response=floating contacts=dark pad, whereas a failing response=short to grounded contact layer→grounded pad=bright pad.

FIGS. 33A-85 depict exemplary cells from a standard cell library. These cells are compatible with the test-enabled fill cells of FIGS. 11-32 above. These exemplary standard cells are depicted, in detail, in the accompanying FIGS. 33A-85. The function of each depicted cell is described below. FIG. 33A provides a layer legend for the figures, with the layers depicted as follows: metal-1/first mask (11); metal-1/second mask(12); via-0 (13); via-1 (14); metal-2 (15); poly-contact (16); active (17); active-contact (18); poly (19); poly-cut (20); and active-cut (21). As persons skilled in the art will appreciate, these cells are intended to be instantiated and used in ways and configurations well known in the art (as described, for example, in: S. Saika, “Standard cell library and semiconductor integrated circuit,” U.S. Pat. No. 8,302,057 B2 (incorporated by reference herein); J. J. Lee, et al., “Standard Cell Placement Technique For Double Patterning Technology,” U.S. Pat. Applic. No. 20130036397 A1 (also incorporated by reference herein); D. D. Sherlekar, “Power Routing in Standard Cell Designs,” U.S. Pat. Applic. No. 20120249182 A1 (also incorporated by reference herein); H. H. Nguyen, et al., “7-tracks standard cell library,” U.S. Pat. No. 6,938,226 (also incorporated by reference herein); P. Penzes, et al., “High-speed low-leakage-power standard cell library,” U.S. Pat. No. 8,079,008 (also incorporated by reference herein); H.-Y. Kim, et al., “Standard cell libraries and integrated circuit including standard cells,” U.S. Pat. No. 8,174,052 (also incorporated by reference herein); and O. M. K. Law, et al., “Standard cell architecture and methods with variable design rules,” U.S. Pat. No. 8,173,491 (also incorporated by reference herein)). Furthermore, as persons skilled in the art will recognize, the dummy poly stripes depicted beyond the right and left edges of each cell boundary are used for DRC checking, and therefore should not be considered a part of the cells themselves. Product ICs constructed using the inventive library are preferably fabricated using commercially available 14 nm fabrication processes.

Reference is made to FIGS. 33A-B, which respectively depict abutting left and right portions of a first exemplary standard cell. This cell implements the logic function of a scan-enabled d-flip-flop with set and inverted output in drive strength 3.

Reference is made to FIGS. 34A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements the logic function of a scan-enabled d-flip-flop with set and inverted output in drive strength 2.

Reference is made to FIGS. 35A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements the logic function of a scan-enabled d-flip-flop with set and inverted output in drive strength 1.

Reference is made to FIGS. 36A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements a scan-enabled d-flip-flop with set in drive strength 3.

Reference is made to FIGS. 37A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements the logic function of a scan-enabled d-flip-flop with set in drive strength 2.

Reference is made to FIGS. 38A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements a scan-enabled d-flip-flop with set in drive strength 1.

Reference is made to FIGS. 39A-B, which respectively depict abutting left and right portions of another standard cell. This implements the logic function of a scan-enabled d-flip-flop with reset and inverted output in drive strength 3.

Reference is made to FIGS. 40A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements a scan-enabled d-flip-flop with reset and inverted output in drive strength 2.

Reference is made to FIGS. 41A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements a scan-enabled d-flip-flop with reset and inverted output in drive strength 1.

Reference is made to FIGS. 42A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements the logic function of a scan-enabled d-flip-flop with reset in drive strength 3.

Reference is made to FIGS. 43A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements a scan-enabled d-flip-flop with reset in drive strength 2.

Reference is made to FIGS. 44A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements the logic function of a scan-enabled d-flip-flop with reset in drive strength 1.

Reference is made to FIG. 45, which depicts another standard cell. This cell implements the logic function of a latch with set and reset in drive strength 3.

Reference is made to FIG. 46, which depicts another standard cell. This cell implements the logic function of a latch with set and reset in drive strength 2.

Reference is made to FIG. 47, which depicts another standard cell. This cell implements the logic function of a latch with set and reset in drive strength 1.

Reference is made to FIG. 48, which depicts another standard cell. This cell implements the logic function of a latch with set in drive strength 3.

Reference is made to FIG. 49, which depicts another standard cell. This cell implements the logic function of a latch with set in drive strength 2.

Reference is made to FIG. 50, which depicts another standard cell. This cell implements the logic function of a latch with set in drive strength 1.

Reference is made to FIG. 51, which depicts another standard cell. This cell implements the logic function of a latch with reset in drive strength 3.

Reference is made to FIG. 52, which depicts another standard cell. This cell implements the logic function of a latch with reset in drive strength 2.

Reference is made to FIG. 53, which depicts another standard cell. This cell implements the logic function of a latch with reset in drive strength 1.

Reference is made to FIG. 54, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 4.

Reference is made to FIG. 55, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 3.

Reference is made to FIG. 56, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 2.

Reference is made to FIG. 57, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 1.

Reference is made to FIG. 58, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 3.

Reference is made to FIG. 59, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 2.

Reference is made to FIG. 60, which depicts another standard cell. This cell implements the logic function of a latch with inverted output in drive strength 1.

Reference is made to FIG. 61, which depicts another standard cell. This cell implements the logic function of a latch with set, reset and inverted clock in drive strength 3.

Reference is made to FIG. 62, which depicts another standard cell. This cell implements the logic function of a latch with set, reset and inverted clock in drive strength 2.

Reference is made to FIG. 63, which depicts another standard cell. This cell implements the logic function of a latch with set, reset and inverted clock in drive strength 1.

Reference is made to FIG. 64, which depicts another standard cell. This cell implements the logic function of a latch with set and inverted clock in drive strength 3.

Reference is made to FIG. 65, which depicts another standard cell. This cell implements the logic function of a latch with set and inverted clock in drive strength 2.

Reference is made to FIG. 66, which depicts another standard cell. This cell implements the logic function of a latch with set and inverted clock in drive strength 1.

Reference is made to FIG. 67, which depicts another standard cell. This cell implements the logic function of a latch with reset and inverted clock in drive strength 3.

Reference is made to FIG. 68, which depicts another standard cell. This cell implements the logic function of a latch with reset and inverted clock in drive strength 2.

Reference is made to FIG. 69, which depicts another standard cell. This cell implements the logic function of a latch with reset and inverted clock in drive strength 1.

Reference is made to FIG. 70, which depicts another standard cell. This cell implements the logic function of a latch with reset, inverted clock and inverted output in drive strength 3.

Reference is made to FIG. 71, which depicts another standard cell. This cell implements the logic function of a latch with reset, inverted clock and inverted output in drive strength 2.

Reference is made to FIG. 72, which depicts another standard cell. This cell implements the logic function of a latch with reset, inverted clock and inverted output in drive strength 1.

Reference is made to FIG. 73, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock and inverted output in drive strength 4.

Reference is made to FIG. 74, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock and inverted output in drive strength 3.

Reference is made to FIG. 75, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock and inverted output in drive strength 2.

Reference is made to FIG. 76, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock and inverted output in drive strength 1.

Reference is made to FIG. 77, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock in drive strength 3.

Reference is made to FIG. 78, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock in drive strength 2.

Reference is made to FIG. 79, which depicts another standard cell. This cell implements the logic function of a latch with inverted clock in drive strength 1.

Reference is made to FIG. 80, which depicts another standard cell. This cell implements the logic function of a two-input, tri-state multiplexor in drive strength 4.

Reference is made to FIG. 81, which depicts another standard cell. This cell implements the logic function of a two-input, tri-state multiplexor in drive strength 2.

Reference is made to FIG. 82, which depicts another standard cell. This cell implements the logic function of a two-input, tri-state multiplexor in drive strength 1.

Reference is made to FIGS. 83A-B, which respectively depict abutting left and right portions of another standard cell. This cell implements the logic function of a two-input, tri-state multiplexor with inverted output in drive strength 4.

Reference is made to FIG. 84, which depicts another standard cell. This cell implements the logic function of a two-input, tri-state multiplexor with inverted output in drive strength 2.

Reference is made to FIG. 85, which depicts another standard cell. This cell implements the logic function of a two-input, tri-state multiplexor with inverted output in drive strength 1.

As persons skilled in the art will appreciate, the exemplary flip-flop, latch, and mux designs depicted in FIGS. 33A-85 achieve a significant improvement (e.g., reduction of at least one poly stripe), as compared to competing designs.

FIG. 86 depicts the prior-art “step and scan” and “swathing” techniques.

FIG. 87 depicts a prior-art beam scanning/shaping apparatus.

FIG. 88 shows examples of the beam shapes that can be realized using the column of FIG. 87.

FIG. 89 depicts an exemplary semiconductor wafer that is typically circular and broken up into identical dies, and further depicts an example case where all of the test structures are located in the scribe areas of the die.

FIG. 90 illustrates a series of test structures laid out with their pads in a column, where a spot of the electron beam scans over the pads by the relative motion of the wafer to the spot.

FIG. 91 shows an illustration of an electron spot shaped in a non-circular manner to match the size and shape of the pad, so as to maximize the electron current that is delivered to the pad.

FIG. 92 shows another illustration of pad shapes being sized according to the amount of charge that needs to be delivered to the test structures, wherein test structures needing more charge have longer pads along the scanning direction of the beam to increase the beam dwell time on the pad.

FIG. 93 depicts a scenario in which the beam moves fast if there is a long stretch with no pads to charge, but with constant velocity and slower in populated regions to allow more charging of the pads of the test structures.

FIG. 94 shows test structures laid out on either sides of the pads, which allows a larger number of test structures to be scanned with a single pass of the beam on the wafer.

FIG. 95 shows how solid pads may be split into finer lines or alternate shapes so that their layout will be compatible with the design rules of the semiconductor process. Reference is now made to FIG. 96, which depicts a VC DUT with size and shape to accommodate non-circular incident e-beams for readout in a single spot measurement, with a pad group designed with only alternating lines connected the DUT, and the remaining lines of pad connected to floating or ground such that their polarity is opposite to that of the functioning DUT.

For a functioning DUT, the pad lines will appear as alternating bright/dark, whereas for a non-functioning DUT (i.e. one that has failed), pads are all bright or all dark. The advantage here is that the “net” gray level for all non-defective DUTs is effectively always the same, and the image computer can use the same thresholds for the detection of all defective DUTs. This simplifies the software algorithm and the hardware of the image computer.

Reference is now made to FIG. 97, which conceptually illustrates one embodiment of a VC DUT in accordance with certain aspects of the invention. Pads are read off by using a large spot size e-beam tool, either by a single pixel measurement (i.e., single analog readout) or N analog values at same location (i.e., N-sample digital-averaging could be used to improve SNR).

The beam and pad are designed to have more or less the same footprint. In this case, the X/Y aspect ratio ˜1. Beam is square shaped to match the pad, but could also be circular with similar size. Pictograph shows four pads, but the invention applies to one or multiple pads equivalently.

Reference is now made to FIG. 98, which conceptually illustrates another embodiment of a VC DUT in accordance with certain aspects of the invention. Pads are read off by using a large spot size e-beam tool, either by a single pixel measurement (i.e., single analog readout) or N analog values at same location (i.e., N-sample digital-averaging could be used to improve SNR). Overall, pad and beam have similar footprint on wafer. However, to accommodate a non-symmetric beam (X/Y aspect ratio >3) while meeting semiconductor layout design rules, the pad is split into array of narrow horizontal lines. Pictograph shows one pad, but the invention applies to one or multiple pads equivalently.

Reference is now made to FIG. 99, which conceptually illustrates another embodiment of a VC DUT in accordance with certain aspects of the invention. Pads are optimized for line-shaped beam. X/Y Aspect ratio of pads and beam is greater than 3. Pads are read off like a bar-code scanner, with the polarity of each pad being read off in fewer than 10 pixels. Pictograph shows four pads, but the invention applies to one or multiple pads equivalently.

Claims

1. An IC fabrication process, comprising at least the following steps:

subjecting a product IC wafer to initial fabrication steps;

obtaining e-beam excited measurements, without continuously scanning, from a plurality of test structures by selectively sampling fewer than ten pixels from an e-beam pad associated with each of said test structures; and, based, at least in part, on measurements obtained from said test structures, selectively subjecting the wafer to additional fabrication steps.

2. An IC fabrication process, as defined in claim 1, wherein obtaining measurements comprises selectively targeting e-beam target pads having an asymmetric aspect ratio.

3. An IC fabrication process, as defined in claim 1, wherein obtaining measurements involves obtaining only a single pixel measurement from each targeted e-beam pad.

4. An IC fabrication process, as defined in claim 1, wherein selectively subjecting comprises determining whether to rework one or more of the initial fabrication steps.

5. An IC fabrication process, as defined in claim 1, wherein selectively subjecting comprises determining whether or not to perform the additional fabrication steps.

6. An IC fabrication process, comprising at least the following steps:

subjecting a product IC wafer to initial fabrication steps;

obtaining e-beam excited measurements from a plurality of test structures by selectively targeting, using an e-beam spot with an elongated major axis, an e-beam pad associated with each of said test structures; and,

based, at least in part, on measurements obtained from said test structures, selectively subjecting the wafer to additional fabrication steps.

7. An IC fabrication process, as defined in claim 6, wherein each of the targeted e-beam pads has at least one of its dimensions matched to the elongated major axis of the e-beam spot, so as to maximize scanning efficiency.

8. An IC fabrication process, as defined in claim 6, wherein each of the targeted e-beam pads has a first one of its dimensions matched to the elongated major axis of the e-beam spot, and wherein at least some of the targeted e-beam pads vary in a second dimension perpendicular to said first dimension.

9. An IC fabrication process, as defined in claim 6, wherein each of the targeted e-beam pads is positioned along a linear scan line, and wherein the elongated major axis of the e-beam spot is oriented perpendicular to the scan line.

10. An IC fabrication process, as defined in claim 6, wherein obtaining measurements involves obtaining fewer than ten pixel measurements from each targeted e-beam pad.

11. An IC fabrication process, as defined in claim 10, wherein obtaining measurements involves obtaining only a single pixel measurement from each targeted e-beam pad.

12. An IC fabrication process, as defined in claim 6, wherein selectively subjecting comprises determining whether to rework one or more of the initial fabrication steps.

13. An IC fabrication process, as defined in claim 6, wherein selectively subjecting comprises determining whether or not to perform the additional fabrication steps.

14. An IC fabrication process, comprising at least the following steps:

subjecting a product IC wafer to initial fabrication steps;

obtaining e-beam excited measurements from a plurality of test structures by selectively targeting, along a linear scan direction, an e-beam pad associated with each of said test structures, wherein each targeted e-beam pad comprises a plurality of electrically connected, elongated metal segments; and,

based, at least in part, on measurements obtained from said test structures, selectively subjecting the wafer to additional fabrication steps.

15. An IC fabrication process, as defined in claim 14, wherein each of the targeted e-beam pads has at least two elongated metal segments that are identical in size and shape.

16. An IC fabrication process, as defined in claim 14, wherein obtaining measurements involves obtaining fewer than ten pixel measurements from each targeted e-beam pad.

17. An IC fabrication process, as defined in claim 16, wherein obtaining measurements involves obtaining only a single pixel measurement from each targeted e-beam pad.

18. An IC fabrication process, as defined in claim 14, wherein obtaining measurements involves selectively targeting, using an e-beam spot with an elongated major axis oriented perpendicular to the linear scan direction.

19. An IC fabrication process, as defined in claim 14, wherein selectively subjecting comprises determining whether to rework one or more of the initial fabrication steps.

20. An IC fabrication process, as defined in claim 14, wherein selectively subjecting comprises determining whether or not to perform the additional fabrication steps.