Abstract: A motion sensing system uses high-voltage biasing to achieve high resolution with ultra-low power. The motion sensing system consists of a motion sensor, a readout circuit, and a high-voltage bias circuit to generate the optimized bias voltage for the motion sensor. By using the high-voltage bias, the signal from the motion sensor is raised above the readout circuit's noise floor, eliminating the power-hungry amplifier and signal-chopping used in conventional motion sensing systems. The bias circuit, while producing the programmable bias voltages for the motion sensor, also compensates for the process mismatch raised by the high voltage biases.

Abstract: A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Abstract: An amplifier is presented with a sample and average common mode feedback resistor. The amplifier circuit includes a feedback capacitor and a feedback resistor in parallel with the feedback capacitor, where the feedback capacitor and the feedback resistor form part of the negative feedback path for the amplifier. Of note, the feedback resistor is comprised of a low pass filter in series with a switched capacitor resistor, such that the low pass filter is electrically coupled to the output of the amplifier circuit and the switched capacitor resistor is electrically coupled to the inverting input of the amplifier circuit. The amplifier circuit further includes a control circuit interfaced with switches of the switched capacitor resistor. The high pass corner of the switched capacitor resistor is preferably lower than corner of the low pass filter.

Abstract: A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices.

Abstract: An analog-to-digital converter (ADC) circuit is present, which is particularly suitable for use in an image sensor. The ADC circuit includes a comparator and a digital-to-analog converter (DAC) circuit. The DAC circuit includes two or more charge paths electrically coupled to the output node. Each charge path is formed by one or more charge-injection cells electrically coupled via a gain capacitor to the output node, and a charge conversion capacitor electrically coupled in parallel with the one or more charge-injection cells. Each charge-injection cell is configured to transfer a fixed amount of charge from a charge source to an associated charge path and includes at least one switch configured to isolate the charge source from the output node.

Abstract: A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer ?/? of 0.26% and wafer-to-wafer ?/? of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from ?40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.

Abstract: An intraocular pressure sensor is presented that achieve very low power consumption. The intraocular pressure sensor takes the form of an implantable assembly configured to be implanted in an eye of a subject. Specifically, the implantable assembly is comprised of a capsular tension ring attached to a flexible printed circuit board. The flexible printed circuit board includes a cutout that is sized to encircle the pupil of the eye and is C shaped. One or more electrical components are also mounted onto the flexible printed circuit board. One such component is a voltage reference generator that is implemented by a circuit which provides inherently low process variation and low power consumption.

Abstract: An environmental sensor implementing a sleep mode timer with an oscillator circuit suitable for low power applications is presented. The oscillator circuit includes a plurality of timer stages cascaded in series with each other. Each timer circuit includes a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors. Each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the voltages oscillate. A complementary-to-absolute temperature (“CTAT”) voltage generator is configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature.

Abstract: A self-oscillating DC-DC converter structure is proposed in which an oscillator is completely internalized within the switched-capacitor network. This eliminates power overhead of clock generation and level shifting and enables higher efficiency at lower power levels. Voltage doublers are cascaded to form a complete energy harvester with a wide load range from 5 nW to 5 ?W and self-starting operation down to 140 mV. Because each doubler is self-oscillating, the frequency of each stage can be independently modulated, thereby optimizing the overall conversion efficiency.

Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

Abstract: A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.

Abstract: An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 ?m CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (?10° C. to 90° C.) and 1%/V line sensitivity.

Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Abstract: An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.

Abstract: A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.

Abstract: An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 ?m CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (?10° C. to 90° C.) and 1%/V line sensitivity.

Abstract: An improved oscillation driver circuit for use in an integrated circuit in combination with an oscillation element. An amplification element is adapted to receive an oscillator output, and to generate an amplified oscillator output. A pulse generator receives the amplified oscillator output and generates positive and negative pulsed outputs substantially in phase with the oscillator output. A driver element is adapted to drive the oscillator input in response to the pulsed outputs.

Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.