Patents by Inventor Dennis Sylvester
Dennis Sylvester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9639107Abstract: A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.Type: GrantFiled: March 19, 2015Date of Patent: May 2, 2017Assignee: The Regents Of The University Of MichiganInventors: David T. Blaauw, Dennis Sylvester, Myungjoon Choi, Inhee Lee, Taekwang Jang
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Publication number: 20160291129Abstract: A matched filter is provided for signal processing applications such as GNSS and RADAR. The filter includes a plurality of correlator cells configured to receive a digital signal and are arranged so that values of the digital signal can be shifted amongst the plurality of correlator cells. Each correlator cell includes a correlator circuit, a data source and a current source. The correlator circuit is configured to receive a value from the digital signal and operates to correlate the value with a value of the known pattern stored in the data store. The current source is interfaced with the correlator circuit and selectively sources current based on the correlation operation performed by the correlator circuit; and an output circuit is coupled to each of the plurality of correlator cell and operates to generate an output which is correlated to current that is being source collectively by the current sources.Type: ApplicationFiled: February 9, 2015Publication date: October 6, 2016Inventors: Michael B. HENRY, Dennis SYLVESTER, Bharan GIRIDHAR, David T. BLAAUW, Laura FREYMAN, David Alan FICK
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Patent number: 9385692Abstract: An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 ?m CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (?10° C. to 90° C.) and 1%/V line sensitivity.Type: GrantFiled: March 18, 2015Date of Patent: July 5, 2016Assignee: The Regents Of The University Of MichiganInventors: David T. Blaauw, Dennis Sylvester, Seok Hyeon Jeong
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Publication number: 20160048755Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Inventors: Laura Freyman, David T. Blaauw, Dennis Sylvester, Michael B. Henry, David Alan Fick
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Patent number: 9147443Abstract: An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.Type: GrantFiled: May 16, 2012Date of Patent: September 29, 2015Assignee: The Regents Of The University of MichiganInventors: Scott Hanson, Dennis Sylvester, David Blaauw
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Publication number: 20150270804Abstract: An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 ?m CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (?10° C. to 90° C.) and 1%/V line sensitivity.Type: ApplicationFiled: March 18, 2015Publication date: September 24, 2015Inventors: David T. Blaauw, Dennis Sylvester, Seok Hyeon Jeong
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Publication number: 20150268689Abstract: A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.Type: ApplicationFiled: March 19, 2015Publication date: September 24, 2015Inventors: David T. Blaauw, Dennis Sylvester, Myungjoon Choi, Inhee Lee, Taekwang Jang
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Publication number: 20150207460Abstract: An improved oscillation driver circuit for use in an integrated circuit in combination with an oscillation element. An amplification element is adapted to receive an oscillator output, and to generate an amplified oscillator output. A pulse generator receives the amplified oscillator output and generates positive and negative pulsed outputs substantially in phase with the oscillator output. A driver element is adapted to drive the oscillator input in response to the pulsed outputs.Type: ApplicationFiled: February 15, 2013Publication date: July 23, 2015Inventors: Dongmin Yoon, David T. Blaauw, Dennis Sylvester, Scott Hanson
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Publication number: 20150085406Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.Type: ApplicationFiled: September 19, 2014Publication date: March 26, 2015Inventors: Yen-po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, Dennis Sylvester, David Blaauw
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Patent number: 8564275Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.Type: GrantFiled: June 25, 2010Date of Patent: October 22, 2013Assignee: The Regents of the University of MichiganInventors: Mingoo Seok, Dennis Sylvester, David Blaauw, Scott Hanson, Gregory Chen
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Patent number: 8335122Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.Type: GrantFiled: November 12, 2008Date of Patent: December 18, 2012Assignee: The Regents of the University of MichiganInventors: Ronald George Dreslinski, Jr., Gregory Kengho Chen, Trevor Nigel Mudge, David Theodore Blaauw, Dennis Sylvester
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Publication number: 20120293212Abstract: An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Scott Hanson, Dennis Sylvester, David Blaauw
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Patent number: 8103981Abstract: An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.Type: GrantFiled: September 25, 2009Date of Patent: January 24, 2012Assignees: The Regents of the University of California, The Regents of the University of MichiganInventors: Andrew B. Kahng, Puneet Gupta, Dennis Sylvester, Jie Yang
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Publication number: 20100327842Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.Type: ApplicationFiled: June 25, 2010Publication date: December 30, 2010Applicant: The Regents of The University of MichiganInventors: Mingoo Seok, Dennis Sylvester, David Blaauw, Scott Hanson, Gregory Chen
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Publication number: 20100023917Abstract: An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.Type: ApplicationFiled: September 25, 2009Publication date: January 28, 2010Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Andrew B. Kahng, Puneet Gupta, Dennis Sylvester, Jie Yang
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Patent number: 7614032Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.Type: GrantFiled: December 11, 2006Date of Patent: November 3, 2009Assignees: The Regents of the Univerisity of California, The Regents of the University of MichiganInventors: Andrew B. Kahng, Puneet Gupta, Dennis Sylvester, Jie Yang
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Publication number: 20090138658Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.Type: ApplicationFiled: November 12, 2008Publication date: May 28, 2009Applicant: The Regents of the University of MichiganInventors: Ronald George Dreslinski, JR., Gregory Kengho Chen, Trevor Nigel Mudge, David Theodore Blaauw, Dennis Sylvester
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Publication number: 20070168903Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.Type: ApplicationFiled: December 11, 2006Publication date: July 19, 2007Inventors: Andrew Kahng, Puneet Gupta, Dennis Sylvester, Jie Yang
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Patent number: 7149999Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for a mask design layout for a predetermined parametric yield with a minimum total correction cost. The mask design layout is corrected at a determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the mask design layout that are critical for obtaining a desired performance yield are corrected, thereby reducing total cost of correction of the mask design layout.Type: GrantFiled: February 25, 2004Date of Patent: December 12, 2006Assignees: The Regents of the University of California, The Regents of the University of MichiganInventors: Andrew B. Kahng, Puneet Gupta, Dennis Sylvester, Jie Yang
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Publication number: 20060018171Abstract: There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.Type: ApplicationFiled: June 13, 2005Publication date: January 26, 2006Applicant: ARM LimitedInventors: Todd Austin, David Blaauw, Trevor Mudge, Dennis Sylvester, Krisztian Flautner