Abstract: A new magnetic RAM cell device is achieved. The device comprises a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A diode is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

Abstract: A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

Abstract: In magnetic memories it is important to be able to switch the states of the memory elements using minimal power i.e. external fields of minimal intensity. This has been achieved by giving each memory element an easy axis whose direction parallels its minimum surface dimension. Then, when the magnetic state of the element is switched by rotating its direction of magnetization, said rotation is assisted, rather than being opposed, by the crystalline anisotropy. Consequently, relative to the prior art, a lower external field is required to switch the state of the element.

Abstract: Applicants disclose a method for producing a magnetic transducer with a inductive write head having a multilayer coil with a high aspect ratio and a short yoke. A damascene process is used for two coil layers and a conventional process for the third coil layer. The process of the invention allows a seed layer for the coil to be deposited on the side walls of the trenches for the first and second coil layers. In one embodiment the seed layer for the coil is preceded by an adhesion layer.

Abstract: A method of forming a mask for bombardment of a semiconductor substrate with high energy particles and a mask formed thereby are provided. A patterned layer of a blocking material is formed over a mask substrate to define a high energy particle bombardment mask pattern. The blocking material has sufficient thickness in the mask pattern to substantially shield the semiconductor substrate from selected high energy particles in areas overlapped by the mask pattern when the mask is aligned over the semiconductor substrate. The mask includes a mask substrate having a patterned layer of blocking material formed thereon to define a high energy particle bombardment mask pattern. The blocking material has sufficient thickness in the mask pattern to substantially shield the semiconductor substrate from selected high energy particles in areas of the semiconductor substrate overlapped by the mask pattern when the mask is aligned over the semiconductor substrate.

Abstract: A Damascene process is provided for manufacturing a coil structure for a magnetic head. During the manufacturing process, an insulating layer is initially deposited after which a photoresist layer is deposited. A silicon dielectric layer is then deposited on the photoresist layer. After masking the silicon dielectric layer, at least one channel is etched in the photoresist layer and the silicon dielectric layer. Then, a conductive seed layer is deposited in the at least one channel. The at least one channel is then ready to be filled with a conductive material and chemically/mechanically polished to define a coil structure.

Abstract: A Damascene process is provided for manufacturing a coil structure for a magnetic head. During the manufacturing process, an insulating layer is initially deposited after which a photoresist layer is deposited. A silicon dielectric layer is then deposited on the photoresist layer. After masking the silicon dielectric layer, at least one channel is etched in the photoresist layer and the silicon dielectric layer. Then, a conductive seed layer is deposited in the at least one channel. The at least one channel is then ready to be filled with a conductive material and chemically/mechanically polished to define a coil structure.

Abstract: The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path. As a consequence of such radiation damage the resistivity of the semiconductor in the irradiated area is increased by several orders of magnitude, causing it to become semi-insulating. Semi-insulating regions of this type are effective as electrically isolating regions and can be used, for example, to decouple analog from digital circuits or to maintain high Q in integrated inductors after these devices have been made. The radiation used could be electromagnetic (such as X-rays or gamma rays) or it could comprise energetic particles such as protons, deuterons, etc. Confinement of the beam to local regions within the semiconductor is accomplished by means of suitable masks.

Abstract: The present invention includes a plurality of thin film magnetic heads which are arranged in a linear array with a spacing D between adjacent heads. The pole pieces of the magnetic heads are positioned in a side by side relationship in contrast to the normal pancake type of magnetic head. The linear array is angled at a skew angle .theta. with respect to the direction of travel of the magnetic medium. The track pitch is then D sin .theta.. The track width is substantially equal to the thickness of the pole tips P1T and P2T of the magnetic heads. This thickness can be in the order of 3 .mu.m. With such a pole tip thickness the track pitch of each magnetic head in the linear array can be 3-4 .mu.m. A plurality of narrow data tracks can then be provided with minimum pitch by a corresponding number of magnetic heads. The write signals are simultaneously fed to the heads or the read signals are simultaneously fed to the heads. This allows high data rates to be processed.

Abstract: A nonvolatile magnetoresistive (MR) storage device comprising a plurality of MR storage elements, each comprising a substrate and a multilayered structure including two thin film layers of ferromagnetic material separated by a thin layer of nonmagnetic metallic conducting material. The magnetization easy axis of both ferromagnetic layers in each storage element is oriented substantially lengthwise of the storage elements and substantially parallel to the direction of an applied sense current. The magnetization direction of one of the ferromagnetic layers is fixed in a direction substantially lengthwise of the storage elements, and the magnetization direction of the other layer is free to switch between two digital states in which the magnetization is substantially parallel or substantially antiparallel to the magnetization direction in the one layer.

Abstract: A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.

Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.

Abstract: High-speed low-power emitter coupled logic (ECL) and non-threshold logic (NTL) circuits are disclosed wherein an ac-coupled complementary push-pull output stage is utilized. The circuits utilize two capacitors to couple an ac-pulse derived from a replica of an input signal to the bases of the complementary PNP-NPN push-pull transistors to provide a large transient current, thus realizing high-speed operation with very low dc power dissipation. The coupling scheme allows a very low switch current to be used for the logic (current switch) stage to maintain the proper logic levels while avoiding the impact on the switching speed by the large pull-up resistors of the logic stage.

Abstract: Apparatus for a bipolar active semiconductor magnetic field sensor that has a higher sensitivity than semiconductor field sensors presently existing in the art. Specifically, the inventive sensor utilizes a semiconductor structure containing a single emitter layer, a single base layer that is overlaid over the emitter layer and two separate oppositely situated collectors located above the base layer. A bias lateral majority carrier flow is established, in preferably and respectively both the base and emitter layers (electrons in the emitter, holes in the base), that flows in opposite directions in these layers and is oriented normal (transverse) both to the direction of transistor current and to the direction of a magnetic field that is to be detected. When the magnetic field is applied to the sensor, this field imparts a Lorentz force to these carriers which causes these majority carriers to deflect in the same direction in both the emitter and base layers, respectively.

Abstract: This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to .alpha.-particle radiation is reduced by permitting the potential at the common-emitter node of the cross-coupled transistors of the memory cell to swing freely. Still more particularly, it relates to a SRAM cell wherein the common-emitter node of the cell is decoupled from a heavily capacitively loaded word line with its common constant current source by means of a constant current source or current mirror disposed in each cell between the common-emitter node and the word line.

Abstract: Isolation regions in a semiconductor substrate are formed by covering at least one of the surfaces within a trench within the substrate with non-nucleating material, providing a layer of nucleating material on at least one surface of the non-nucleating material and then filling the trench with polycrystalline silicon or epitaxial silicon or both.

Abstract: An integrated circuit containing a refractory metallic silicide beneath a field isolation region and in electrical contact with electrical conductive regions of active impurity dopants in a semiconductive substrate; and process for the fabrication thereof.

Abstract: A vertical pair of complementary, bipolar transistors is disclosed which includes a semiconductor substrate of one conductivity type and a pair of dielectric isolation regions disposed in contiguous relationship with the substrate. An injector region of opposite conductivity type is disposed between the pair of isolation regions. A pair of heavily doped, polycrystalline, semiconductor regions of the one conductivity type is disposed over and in registry with the pair of isolation regions. Similarly, a single crystal, semiconductor region of the one conductivity type is disposed over and in registry with the injector region. Finally, a first zone of opposite conductivity type is disposed in the single crystal region and a second zone of the one conductivity type is disposed in the first zone.

Abstract: A semiconductor circuit in which a plurality of transistors is provided, the collector regions/contacts and the base regions/contacts of the transistors being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors of these transistors can be butted to a field oxide to reduce the extrinsic base area and to minimize excess charge storage in the base region. The base contacts, whether polysilicon or metal, etc. provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow.