Abstract: A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.

Abstract: A receiver includes a sampling circuit configured to sample a comparison result between an input signal and a plurality of threshold voltages according to a sampling clock signal; a clock controller configured to generate the sampling clock signal according to a clock control signal; and a control circuit configure to generate the clock control signal and the plurality of threshold voltages according to a target value and an output of the sampling circuit. The control circuit operates to control a ratio of a magnitude of a main cursor of the input signal and a magnitude of a pre-cursor intersymbol interference to be the target value.

Abstract: There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

Abstract: A receiver includes an equalization circuit configured to output a data sample signal and an edge sample signal by sampling a data input signal according to clock signal, and to perform an equalization operation according to the data sample signal and the edge sample signal; and a clock gate circuit configured to select the clock signals from among a plurality of multi-phase clock signals according to a selection signal.

Abstract: A semiconductor device includes a first switch coupling a first switch coupling a first power source and a first node according to a first control signal; a sense amplifier coupled between the first node and a second node and performing a sensing operation; a second switch coupling a second power source and the second node according to a second control signal; and a sense amplifier control circuit providing the first control signal and the second control signal. The sense amplifier control circuit controls the second control signal so that a voltage of the second node reaches a shift voltage higher than a voltage of the second power source during a first sensing period of the sensing operation and a bias current flows through the second node during a second sensing period of the sensing operation. The sensing period is subsequent to the first sensing period.

Abstract: A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

Abstract: Provided is a method and an apparatus for optimizing memory power and provide a method and an apparatus for optimizing memory power by minimizing power consumed by pins of a memory by using an SBR pattern. The method of optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method includes: setting a ratio and sizes of a pull-up transistor and a pull-down transistor included in a driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern.

Abstract: A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.

Abstract: A receiver includes a sampling circuit configured to sample a comparison result between an input signal and a plurality of threshold voltages according to a sampling clock signal; a clock controller configured to generate the sampling clock signal according to a clock control signal; and a control circuit configure to generate the clock control signal and the plurality of threshold voltages according to a target value and an output of the sampling circuit. The control circuit operates to control a ratio of a magnitude of a main cursor of the input signal and a magnitude of a precursor intersymbol interference to be the target value.

Abstract: A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.

Abstract: An accelerator includes a key matrix register configured to store a key matrix, a query vector register configured to store a query vector; and a preprocessor configured to calculate similarities between the query vector and the key matrix.

Abstract: Provided is a method and an apparatus for optimizing memory power and provide a method and an apparatus for optimizing memory power by minimizing power consumed by pins of a memory by using an SBR pattern. The method of optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method includes: setting a ratio and sizes of a pull-up transistor and a pull-down transistor included in a driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern.

Abstract: A semiconductor device includes a first switch coupling a first switch coupling a first power source and a first node according to a first control signal; a sense amplifier coupled between the first node and a second node and performing a sensing operation; a second switch coupling a second power source and the second node according to a second control signal; and a sense amplifier control circuit providing the first control signal and the second control signal. The sense amplifier control circuit controls the second control signal so that a voltage of the second node reaches a shift voltage higher than a voltage of the second power source during a first sensing period of the sensing operation and a bias current flows through the second node during a second sensing period of the sensing operation. The sensing period is subsequent to the first sensing period.

Abstract: A display apparatus including a display panel, a touch sensing unit including first and second transmission touch lines, and a touch driving circuit to apply first and second touch driving signals to the first and second transmission touch lines, respectively, in which the touch driving circuit includes a first switch group including a first sharing switch device having one end connected to the first transmission touch line, and a second switch group including a second sharing switch device having two ends respectively connected to the second transmission touch line and another end of the first sharing switch device, and the touch driving circuit is configured to turn on the sharing switch devices during a first period such that the touch driving signals have a first voltage level, and turn on the sharing switch devices during a second period such that the touch driving signals have a second voltage level.

Abstract: A driving circuit includes an input circuit slice configured to convert a data signal into a first data signal and a second data signal having different DC components. The driving circuit also includes a driver slice configured to output driving current at an output node by generating push current or pull current according to the first data signal and the second data signal, wherein a magnitude of the push current or the pull current is variable.

Abstract: A receiver includes an equalization circuit configured to output a data sample signal and an edge sample signal by sampling a data input signal according to clock signal, and to perform an equalization operation according to the data sample signal and the edge sample signal; and a clock gate circuit configured to select the clock signals from among a plurality of multi-phase clock signals according to a selection signal.

Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.

Abstract: A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source.

Abstract: A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source.

Abstract: A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.