Abstract: There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

Abstract: Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver (20) generating waveform including data to be transmitted; and an FFE driver block (40) connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.

Abstract: A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.

Abstract: The present disclosure relates to an adaptation method for data level (dLev) or data swing detection in a high-speed link system for multi-level (e.g. PAM-4) signaling. Provided are a receiver and a receiving method in which when a swing range of data received as an input is changed according to a channel condition, reference levels of data/swing detection samplers are not adaptively controlled, but the reference levels are fixed and a variable gain amplifier (VGA) is adaptively controlled for response to the change. Through the present disclosure, offset calibration of the data/swing detection samplers is more accurately performed and lower bit error rate (BER) is thus achieved.

Abstract: A clock and data recovery (CDR) device includes a data sampler configured to output a data signal by sampling an input signal according to a first clock signal; an edge sampler configured to output an edge signal by sampling the input signal according to a second clock signal, the second clock signal having substantially the same frequency as the first clock signal and having substantially an opposite phase to the first clock signal; an error detection circuit configured to identify a plurality of patterns based on the data signal and the edged signal and generate an error signal according to occurrence frequencies of the identified plurality of patterns; and an oscillation control circuit configured to generate a first oscillation control signal to control an oscillator generating the first and second clock signal according to the error signal.

Abstract: A display apparatus including a display panel, a touch sensing unit including first and second transmission touch lines, and a touch driving circuit to apply first and second touch driving signals to the first and second transmission touch lines, respectively, in which the touch driving circuit includes a first switch group including a first sharing switch device having one end connected to the first transmission touch line, and a second switch group including a second sharing switch device having two ends respectively connected to the second transmission touch line and another end of the first sharing switch device, and the touch driving circuit is configured to turn on the sharing switch devices during a first period such that the touch driving signals have a first voltage level, and turn on the sharing switch devices during a second period such that the touch driving signals have a second voltage level.

Abstract: The present invention relates to an encoding apparatus for multi-level signaling, the encoding apparatus including: a candidate pattern generator (1) generating a set of candidate patterns from input data by using symbol-based inversion; a controller (2) generating a cumulated disparity value that is a result of calculating disparity indicating a degree to which transmission data up to previous transmission deviates from DC balance, storing the cumulated disparity value, and determining a transmission control code by using the cumulated disparity value and a set of disparity values that is a result of calculating disparity indicating a degree to which each of the candidate patterns deviates from DC balance; and a data selector (3) selecting one candidate pattern from the set of the candidate patterns as data to be transmitted, according to the determined transmission control code.

Abstract: A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.

Abstract: A clock and data recovery (CDR) device includes a data sampler configured to output a data signal by sampling an input signal according to a first clock signal; an edge sampler configured to output an edge signal by sampling the input signal according to a second clock signal, the second clock signal having substantially the same frequency as the first clock signal and having substantially an opposite phase to the first clock signal; an error detection circuit configured to identify a plurality of patterns based on the data signal and the edged signal and generate an error signal according to occurrence frequencies of the identified plurality of patterns; and an oscillation control circuit configured to generate a first oscillation control signal to control an oscillator generating the first and second clock signal according to the error signal.

Abstract: Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver (20) generating waveform including data to be transmitted; and an FFE driver block (40) connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.

Abstract: A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.

Abstract: A display apparatus includes a display panel; a touch sensing unit (TSU) on the display panel and including first and second transmission touch lines (TTL); and a touch driving circuit (TDC). The TDC applies first and second touch driving signals (TDS) to the first and second TTL, respectively. The TDC includes first and second sharing switch devices (SSD) respectively connected to the first and second TTL. The first and second SSD are connected to each other. The first TDS has a first voltage level during a first period, and the second TDS has a second voltage level different than the first voltage level during the first period. The TDC is configured to turn on the first and second SSD during a second period after the first period such that the first and second TDSs have a voltage level between the first voltage level and the second voltage level.

Abstract: A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.

Abstract: A data receiving circuit may include: a variable delay circuit suitable for generating a delayed strobe signal by delaying a strobe signal; a receiving circuit suitable for sampling data in synchronization with the delayed strobe signal; a phase shift circuit suitable for generating a shifted strobe signal by shifting a phase of the delayed strobe signal; a phase comparison circuit suitable for comparing phases of the data and the shifted strobe signal; and a delay adjusting circuit suitable for adjusting a delay value of the variable delay circuit in response to the phase comparison result of the phase comparison circuit.

Abstract: A transceiver circuit may include: a first NMOS transistor suitable for puffing up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.

Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.

Abstract: A display apparatus includes a display panel, a touch sensing unit, and a touch driving circuit. The touch sensing unit includes a transmission touch line. The touch driving circuit provides a touch driving signal to the transmission touch line. The touch driving circuit may include a switch group and a control switch group. The switch group may include a plurality of switch devices, each of which has one end connected to the transmission touch line. The control switch group may be connected to the other end of at least a portion of the switch devices, include a plurality of control switch devices and a capacitor device, and receive a driving voltage and a ground voltage. The touch driving signal has N voltage levels, where N is a natural number of 3 or more.

Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.

Abstract: A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.

Abstract: In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.