Patents by Inventor Deok-kee Kim

Deok-kee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685913
    Abstract: An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 16, 2020
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-kee Kim, Jae Hong Kim, Seo Woo Nam
  • Patent number: 10607934
    Abstract: A fuse of a semiconductor device may include: a fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 31, 2020
    Assignees: SK hynix Inc., INDUSTRY-ACAMEDIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-Kee Kim, Jae Hong Kim, Seo Woo Nam
  • Publication number: 20200066717
    Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Deok-kee KIM, Honggyun KIM, Jae Hong KIM, Seo Woo NAM
  • Patent number: 10497700
    Abstract: An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 3, 2019
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Deok-kee Kim, Honggyun Kim, Jae Hong Kim, Seo Woo Nam
  • Publication number: 20190088646
    Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.
    Type: Application
    Filed: February 14, 2018
    Publication date: March 21, 2019
    Inventors: Deok-kee KIM, Honggyun KIM, Jae Hong KIM, Seo Woo NAM
  • Publication number: 20190088597
    Abstract: An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.
    Type: Application
    Filed: February 14, 2018
    Publication date: March 21, 2019
    Inventors: Deok-kee KIM, Jae Hong KIM, Seo Woo NAM
  • Publication number: 20190088596
    Abstract: An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and formed with a drain region and a source region in a top thereof corresponding to both sides of the gate metal to form a transistor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.
    Type: Application
    Filed: February 14, 2018
    Publication date: March 21, 2019
    Inventors: Deok-kee KIM, Honggyun KIM, Jae Hong KIM, Seo Woo NAM
  • Publication number: 20190088647
    Abstract: An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.
    Type: Application
    Filed: February 14, 2018
    Publication date: March 21, 2019
    Inventors: Deok-kee KIM, Honggyun KIM, Jae Hong KIM, Seo Woo NAM
  • Publication number: 20180301411
    Abstract: A fuse of a semiconductor device may include: fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.
    Type: Application
    Filed: October 20, 2017
    Publication date: October 18, 2018
    Inventors: Deok-Kee KIM, Jae Hong KIM, Seo Woo NAM
  • Patent number: 9472402
    Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy J. Dalton, Katherina E. Babich, Arpan P. Mohorowala, Harald Okorn-Schmidt
  • Patent number: 9177643
    Abstract: A method for multi-level programming of a phase change memory device includes selecting a word line from multiple word lines and applying multiple bits of data to a bit line of a cell connected to the selected word line. According to the type of data, the method applies a program current to the selected word line or a multi-level program current to word lines adjacent to the selected word line.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: November 3, 2015
    Assignee: Intellectual Discovery Co., Ltd.
    Inventor: Deok Kee Kim
  • Patent number: 9135996
    Abstract: A variable resistance memory device includes a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-kee Kim, Ho Jung Kim
  • Patent number: 9059000
    Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P. Mahorowala, Harald Okorn-Schmidt
  • Patent number: 8963284
    Abstract: A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Deok-Kee Kim
  • Publication number: 20150004802
    Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Deok-kee Kim, Kenneth T. Settlemyer, JR., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy J. Dalton, Katherina E. Babich, Arpan P. Mohorowala, Harald Okorn-Schmidt
  • Publication number: 20140339489
    Abstract: A phase-change memory device is provided. The memory device includes a lower electrode, a phase-change material layer formed on the lower electrode, an upper electrode formed on the phase-change material layer, and a stress insulation film formed to surround the phase-change material layer.
    Type: Application
    Filed: March 18, 2014
    Publication date: November 20, 2014
    Applicant: Intellectual Discovery Co., Ltd.
    Inventor: Deok Kee KIM
  • Publication number: 20140293688
    Abstract: The present disclosure provides a multi-level programming method of a phase-change memory device. The multi-level programming method comprises selecting a word line, where data are to be input, from multiple word lines; applying multiple bits of data to a bit line of a cell connected to the selected word line; applying a program current to the selected word line for programming of first data; applying a program current to the selected word line and applying a multi-level program current lower than the program current to one of word lines adjacent to the selected word line for programming of second data; and applying a program current to the selected word line and applying a multi-level program current lower than the program current to tow of the word lines adjacent to the selected word line for programming of third data.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: Intellectual Discovery Co., Ltd.
    Inventor: Deok Kee KIM
  • Patent number: 8829645
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S Ozcan, Haining S Yang
  • Patent number: 8809142
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S. Ozcan, Haining S. Yang
  • Patent number: 8674475
    Abstract: Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-kee Kim, Jung-hun Sung, Sang-moo Choi, Soo-jung Hwang