Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

Abstract: An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.

Abstract: A fuse of a semiconductor device may include: a fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.

Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

Abstract: An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.

Abstract: An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.

Abstract: An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.

Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

Abstract: An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and formed with a drain region and a source region in a top thereof corresponding to both sides of the gate metal to form a transistor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

Abstract: A fuse of a semiconductor device may include: fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip suitable for extending in the first direction, and with a predetermined distance from the fuse link in a second direction perpendicular to the first direction; and an air channel formed between the fuse link and the dummy strip to contact with the fuse link.

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract: A method for multi-level programming of a phase change memory device includes selecting a word line from multiple word lines and applying multiple bits of data to a bit line of a cell connected to the selected word line. According to the type of data, the method applies a program current to the selected word line or a multi-level program current to word lines adjacent to the selected word line.

Abstract: A variable resistance memory device includes a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell.

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract: A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract: A phase-change memory device is provided. The memory device includes a lower electrode, a phase-change material layer formed on the lower electrode, an upper electrode formed on the phase-change material layer, and a stress insulation film formed to surround the phase-change material layer.

Abstract: The present disclosure provides a multi-level programming method of a phase-change memory device. The multi-level programming method comprises selecting a word line, where data are to be input, from multiple word lines; applying multiple bits of data to a bit line of a cell connected to the selected word line; applying a program current to the selected word line for programming of first data; applying a program current to the selected word line and applying a multi-level program current lower than the program current to one of word lines adjacent to the selected word line for programming of second data; and applying a program current to the selected word line and applying a multi-level program current lower than the program current to tow of the word lines adjacent to the selected word line for programming of third data.

Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.