Abstract: A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.

Abstract: An electrical structure including a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.

Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

Abstract: An electromigration-programmable semiconductor device may be programmed to increase the resistance or to decrease the resistance by selecting the amount of current passed through the electromigration-programmable semiconductor device. The electromigration-programmable semiconductor device comprises an anode, a cathode, and a link, each having a semiconductor portion and a metal semiconductor alloy portion. The metal semiconductor alloy portion of the link comprises two disjoined sub-portions with a gap therebetween. A low programming current fills the gap by electromigrating a small amount of metal semiconductor alloy from the cathode, A high programming current forms a large metal-semiconductor-alloy-deleted area in the cathode to increase the resistance. A tri-state programming is achieved by selecting the programming current level.

Abstract: A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

Abstract: A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

Abstract: A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.

Abstract: A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.

Abstract: Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

Abstract: An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.

Abstract: Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.

Abstract: An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer.

Abstract: A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.

Abstract: An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract: A method for fabricating an eFuse, the method comprising disposing a crystalline silicon eFuse on a substrate having a fuse link portion, a first contact portion, and a second contact portion, wherein the fuse link is oriented parallel to the silicon crystal {110} plane direction, etching the eFuse using crystallographic orientation dependent wet etching in the {110} plane direction such that a corner at a junction of the fuse link an a contact portion is substantially square, operative to increase current density when an electric current flows through the fuse link, and forming a silicide layer atop the eFuse.

Abstract: A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).

Abstract: A layer of semiconductor material is patterned to form a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. A first metal layer is deposited on the patterned semiconductor material layer. A dielectric material layer is deposited and lithographically patterned to cover a middle portion of the fuselink, followed by a deposition of a second metal layer. A thin metal semiconductor alloy is formed in the middle of the fuselink and thick metal semiconductor alloy alloys are formed abutting the thin metal semiconductor alloy alloy. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink. The divergence of electrical current is enhanced at the interfaces due to a sudden change of a cross-sectional area available for current conduction.

Abstract: A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.