Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.

Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

Abstract: Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

Abstract: A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip.