Patents by Inventor Der-Chyang Yeh

Der-Chyang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Surface mount device/integrated passive device on package or device structure and methods of forming
    Patent number: 10141288
    Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu
  • Packages and Packaging Methods for Semiconductor Devices, and Packaged Semiconductor Devices
    Publication number: 20180337163
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su
  • Package Structure and Method of Forming the Same
    Publication number: 20180331069
    Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: Chen-Hua Yu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Hua-Wei Tseng
  • Multi-Stacked Package-on-Package Structures
    Publication number: 20180323150
    Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
  • Dummy Features in Redistribution Layers (RDLS) and Methods of Forming Same
    Publication number: 20180294228
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same
    Publication number: 20180277520
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Package-on-package semiconductor device
    Patent number: 10083940
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
    Publication number: 20180269188
    Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 20, 2018
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Han-Ping Pu
  • Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
    Patent number: 10074631
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su
  • Semiconductor package and method of forming the same
    Patent number: 10062648
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Semiconductor device packages, packaging methods, and packaged semiconductor devices
    Patent number: 10049898
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu, Chien-Fu Tseng
  • Multi-Stacked Package-on-Package Structures
    Publication number: 20180226349
    Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
    Type: Application
    Filed: July 3, 2017
    Publication date: August 9, 2018
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
  • Multi-chip structure and method of forming same
    Patent number: 10037892
    Abstract: A device includes a redistribution layer over a molding compound layer, a first chip over the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer and a second chip over the first chip, the second chip being connected to the first chip through a plurality of bumps, wherein the first chip and the second chip are in the molding compound layer, and wherein a center line of the first chip is not vertically aligned with a center line of the second chip.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Package structure and method of forming the same
    Patent number: 10037963
    Abstract: A package structure and method of forming the same includes: a first package including: a first die; a via adjacent the first die; a molding compound encapsulating the via and at least laterally encapsulating the first die around a perimeter of the first die; and a first redistribution structure extending over the first die and the molding compound; a first integrated passive device (IPD) attached to the first redistribution structure, the first IPD disposed proximate the perimeter of the first die; a second IPD attached to the first redistribution structure, the second IPD disposed distal the perimeter of the first die; and an underfill disposed between the first IPD and the first redistribution structure, the second IPD being free of the underfill.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Chen-Hua Yu, Hsien-Wei Chen, Der-Chyang Yeh
  • Interconnect Structure for Package-on-Package Devices and a Method of Fabricating
    Publication number: 20180211901
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Raised Via for Terminal Connections on Different Planes
    Publication number: 20180211912
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Application
    Filed: July 3, 2017
    Publication date: July 26, 2018
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kou
  • PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180211908
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Application
    Filed: March 27, 2018
    Publication date: July 26, 2018
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Semiconductor package and method of forming the same
    Patent number: 10026704
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Packages with Metal Line Crack Prevention Design
    Publication number: 20180197839
    Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 12, 2018
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • FAN-OUT STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20180174865
    Abstract: A semiconductor structure and a method of forming include a first semiconductor die and a first dummy die over a carrier, wherein a thickness of the first semiconductor die is greater than a thickness of the first dummy die, a first molding compound layer over the carrier, the first molding compound layer extending along sidewalls of the first semiconductor die and the first dummy die and a first interconnect structure over the first molding compound layer, wherein the first interconnect structure comprises a first metal feature electrically coupled to the first semiconductor die and the first molding compound layer is formed between the first dummy die and the first metal feature.
    Type: Application
    Filed: August 16, 2017
    Publication date: June 21, 2018
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Wei-Yu Chen